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|標題:||Analytical Models of Output Voltages and Power Efficiencies for Multistage Charge Pumps||作者:||Hsu, C.P.
|關鍵字:||Analytical model;charge pump;design methodology;output voltage;power;efficiency;circuits||Project:||Ieee Transactions on Power Electronics||期刊/報告no：:||Ieee Transactions on Power Electronics, Volume 25, Issue 6, Page(s) 1375-1385.||摘要:||
Accurate analytical models of the output voltage and the power efficiency of voltage doublers and PMOS charge pumps are derived using dynamic charge transfer waveforms and charge balance methods, respectively. Since the on-resistance of switching devices and the parasitic capacitance can be estimated precisely, the proposed models are more accurate than the other existing models. The model-generated values agree well with simulations and measurements for these two charge pumps using 0.18 mu m CMOS technology. The expressions for the output voltages prove that the PMOS charge pump can provide more output current without a significant increase in the sizes of transistors. Finally, the design methodology that is based on these models is developed to determine the transistor sizes, capacitance, and number of stages for the maximum power efficiency.
|Appears in Collections:||電機工程學系所|
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