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|標題:||Low-Cost Hardware-Sharing Architecture of Fast 1-D Inverse Transforms for H.264/AVC and AVS Applications||作者:||Su, G.A.
|關鍵字:||AVS;fast algorithm;hardware share;H.264/AVC;low cost;2 x 2/4 x 4/8;x 8 inverse transforms||Project:||Ieee Transactions on Circuits and Systems Ii-Express Briefs||期刊/報告no：:||Ieee Transactions on Circuits and Systems Ii-Express Briefs, Volume 55, Issue 12, Page(s) 1249-1253.||摘要:||
In this paper, the fast one-dimensional (1-D) algorithms and their hardware-sharing designs for the 1-D 2 x 2, 4 x 4, and 8 x 8 inverse transforms of H.264/AVC and the 1-D 8 x 8 inverse transform of AVS are proposed with the low hardware cost, especially for the multiple decoding applications in China. By sharing the hardware, the proposed 1-D hardware sharing architecture is realized by adding the offset computations, and it is implemented with the pipelined architecture. Thus, the hardware cost of the proposed sharing architecture is smaller than that of the individual and separate designs. With regular modularity, the proposed sharing architecture is suitable to achieve H.264/AVC and AVS signal processing by VLSI implementations.
|Appears in Collections:||電機工程學系所|
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