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|標題:||Implementations of low-cost hardware sharing architectures for fast 8 x 8 and 4 x 4 integer transforms in H.264/AVC||作者:||Fan, C.P.
|關鍵字:||fast integer transform;hardware share;H.264/AVC||Project:||Ieice Transactions on Fundamentals of Electronics Communications and Computer Sciences||期刊/報告no：:||Ieice Transactions on Fundamentals of Electronics Communications and Computer Sciences, Volume E90A, Issue 2, Page(s) 511-516.||摘要:||
In this paper, novel hardware sharing architectures are proposed for realizations of fast 4 x 4 and 8 x 8 forward/inverse integer transforms in H.264/AVC applications. Based on matrix factorizations, the cost-effective architectures for fast one-dimensional (I-D) 4 x 4 and 8 x 8 forward/inverse integer transforms can be derived through the Kronecker and direct sum operations. By applying the concept of hardware sharing, the proposed hardware schemes for fast integer transforms need a smaller number of shifters and adders than the direct realization architecture, where the direct architecture just implements the individual 4 x 4 and individual 8 x 8 integer transforms independently. With low hardware cost and regular modularity, the proposed hardware sharing architectures can process up to 125 MHz with the cost-effective area and are suitable for VLSI implementations to accomplish the H.264/AVC signal processing.
|Appears in Collections:||電機工程學系所|
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