Please use this identifier to cite or link to this item:
|標題:||LOW-POWER INSTRUCTION ADDRESS BUS CODING WITH XOR-BITS ARCHITECTURE||作者:||Fan, C.P.
|關鍵字:||Bus coding;low-power;instruction address;switching activity;coupling;activity;systems||Project:||Journal of Circuits Systems and Computers||期刊/報告no：:||Journal of Circuits Systems and Computers, Volume 18, Issue 1, Page(s) 45-57.||摘要:||
In this paper, we present an address bus coding method to reduce dynamic power dissipations and delay faults at on-chip applications. The purpose of the proposed new coding technique is to diminish the switching and coupling activities on instruction address busses effectively. The proposed bus coding method is called the exclusive-OR and bus inverter transition signaling (XOR-BITS) code. The XOR-BITS code has four advantages. Firstly, it can save a large number of switching activities. Secondly, it can also save a large number of coupling activities. Thirdly, its architecture belongs to a low-complexity architecture. Finally, its delay is short after optimizations. Experimental results show that the XOR-BITS coding indicates an average reduction in 78.5% switching activities and 21.9% coupling activities on instruction address busses. It surpasses the other address coding methods in total power dissipations when the load capacitance is more than 1 pF/bit with the TSMC 0.13 mu m CMOS technology. For a 50 pF/bit load capacitance, it achieves a 74.9% average reduction in total power dissipations, compared with the un-coded schemes by using seven benchmarks. Similarly, our method also surpasses the other address bus coding methods with the TSMC 0.18 mu m CMOS technology.
|Appears in Collections:||電機工程學系所|
Show full item record
TAIR Related Article
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.