Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/44247
標題: FPGA IMPLEMENTATIONS OF LOW LATENCY AND HIGH THROUGHPUT 4x4 BLOCK TEXTURE CODING PROCESSOR FOR H.264/AVC
作者: Fan, C.P.
范志鵬
Cheng, Y.L.
關鍵字: 4x4 transforms;quantization;fast algorithm;hardware share;low;latency;high throughput;H.264/AVC;transform
Project: Journal of the Chinese Institute of Engineers
期刊/報告no:: Journal of the Chinese Institute of Engineers, Volume 32, Issue 1, Page(s) 33-44.
摘要: 
In this paper, low latency and high throughput texture coding architectures are proposed to realize the 4x4 integer/Hadamard transforms, the quantization (Q), and the inverse-quantization (IQ) schemes for the H.264/AVC application. Based oil matrix operations, the efficient fast two-dimensional (2-D) 4x4 transforms can be derived from the proposed one-dimensional (1-D) fast 4x4 transforms through matrix decompositions. The fast 2-D 4x4 transform designs with the hardware sharing architecture can achieve high throughput and only need one clock cycle latency delay. The proposed cost-effective and hardware sharing fast 2-D 4x4 transform scheme doesn't require the transpose memory and can be applied to the 4CIF 4:2:0 video encoding. The hardware sharing architecture for both of the Q and the IQ is also developed for the low-cost application. With Xilink FPGA verifications, the proposed low-cost 4x4 texture coding scheme, which can be applied to the CIF 4:2:0 30 frames/sec video encoding can process up to 84 MHz with 90 k gate counts. Then the proposed high speed 4x4 texture coding design which can be applied to the 4CIF 4:2:0 30 frames/ sec video encoding, can process tip to 99 MHz with 135 k gate counts. Both of the two proposed texture coding architectures only require 4 clock cycles latency delay which is smaller than the traditional row-column architectures do.
URI: http://hdl.handle.net/11455/44247
ISSN: 0253-3839
DOI: 10.1080/02533839.2009.9671480
Appears in Collections:電機工程學系所

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