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|標題:||Low-power eight-bit SCSDL CLA with a novel split-level charge-sharing differential logic (SCSDL)||作者:||Chang, R.C.
|關鍵字:||low-power;split-level charge-sharing;charge recycling technique;differential;logic families;carry lookahead adder;current switch logic;family||Project:||Journal of Circuits Systems and Computers||期刊/報告no：:||Journal of Circuits Systems and Computers, Volume 16, Issue 3, Page(s) 389-402.||摘要:||
A novel logic family, called Split-Level Charge-Sharing Differential Logic (SCSDL), is proposed in this letter. The SCSDL uses the charge recycling technique to reduce power dissipation of differential logic in the precharge phase. The simulation results show that the SCSDL has the best power-delay product compared to several other differential logic families. An eight-bit carry lookahead adder (CLA) designed using the proposed SCSDL can reduce at least 30.64% of power-delay product compared to DCVSL CLA dissipation. A test chip was fabricated to illustrate the feasibility of the SCSDL circuit.
|Appears in Collections:||電機工程學系所|
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