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|標題:||Compact Layout of On-Chip Transformer||作者:||Hsu, H.M.
|關鍵字:||Coupling factor;geometry mean distance;on-chip transformer;turn ratio;high turn ratio;monolithic transformers;silicon;design;technology;inductors||Project:||Ieee Transactions on Electron Devices||期刊/報告no：:||Ieee Transactions on Electron Devices, Volume 57, Issue 5, Page(s) 1076-1083.||摘要:||
This study develops a compact layout for an on-chip transformer with both wide range of turn ratios and a high coupling coefficient in a small chip area. Analytical formulas are applied to calculate the self-inductances in the design stage. Therefore, six devices with various turn ratios are designed to verify the proposed layout. All devices are fabricated using foundry 130 nm complementary metal-oxide semiconductor technology. Measurements reveal that the proposed transformer has a wide range of n values (1-5.68) and high coupling k values (0.99-0.48) for a chip area of 1002 mu m(2).
|Appears in Collections:||電機工程學系所|
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