Design of an On-Chip Balun With a Minimum Amplitude Imbalance Using a Symmetric Stack Layout

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Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/44409

標題:	Design of an On-Chip Balun With a Minimum Amplitude Imbalance Using a Symmetric Stack Layout
作者:	Hsu, H.M. 許恒銘 Huang, J.S. Chen, S.Y. Lai, S.H.
關鍵字:	Balun;couple line;imbalance;on-chip;marchand balun;mixer
Project:	Ieee Transactions on Microwave Theory and Techniques
期刊/報告no：:	Ieee Transactions on Microwave Theory and Techniques, Volume 58, Issue 4, Page(s) 814-819.
摘要:	This study develops a compact balun layout to minimize amplitude imbalance. Three baluns with different metal layers are fabricated using 0.13-mu m CMOS technology and their imbalance performance evaluated. Measurement made using eight metal layers in coil windings at a particular layout reveal that the proposed device exhibits minimal amplitude and phase imbalance of 0.2 dB and +/-0.5 degrees with a chip outer dimension of 100 mu m.
URI:	http://hdl.handle.net/11455/44409
ISSN:	0018-9480
DOI:	10.1109/tmtt.2010.2041590
Appears in Collections:	電機工程學系所

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