Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/44409
DC FieldValueLanguage
dc.contributor.authorHsu, H.M.en_US
dc.contributor.author許恒銘zh_TW
dc.contributor.authorHuang, J.S.en_US
dc.contributor.authorChen, S.Y.en_US
dc.contributor.authorLai, S.H.en_US
dc.date2010zh_TW
dc.date.accessioned2014-06-06T08:12:15Z-
dc.date.available2014-06-06T08:12:15Z-
dc.identifier.issn0018-9480zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/44409-
dc.description.abstractThis study develops a compact balun layout to minimize amplitude imbalance. Three baluns with different metal layers are fabricated using 0.13-mu m CMOS technology and their imbalance performance evaluated. Measurement made using eight metal layers in coil windings at a particular layout reveal that the proposed device exhibits minimal amplitude and phase imbalance of 0.2 dB and +/-0.5 degrees with a chip outer dimension of 100 mu m.en_US
dc.language.isoen_USzh_TW
dc.relationIeee Transactions on Microwave Theory and Techniquesen_US
dc.relation.ispartofseriesIeee Transactions on Microwave Theory and Techniques, Volume 58, Issue 4, Page(s) 814-819.en_US
dc.relation.urihttp://dx.doi.org/10.1109/tmtt.2010.2041590en_US
dc.subjectBalunen_US
dc.subjectcouple lineen_US
dc.subjectimbalanceen_US
dc.subjecton-chipen_US
dc.subjectmarchand balunen_US
dc.subjectmixeren_US
dc.titleDesign of an On-Chip Balun With a Minimum Amplitude Imbalance Using a Symmetric Stack Layouten_US
dc.typeJournal Articlezh_TW
dc.identifier.doi10.1109/tmtt.2010.2041590zh_TW
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.fulltextno fulltext-
item.cerifentitytypePublications-
item.grantfulltextnone-
item.languageiso639-1en_US-
item.openairetypeJournal Article-
Appears in Collections:電機工程學系所
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