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|標題:||A CMOS clock and data recovery circuit with a half-rate three-state phase detector||作者:||Yang, C.Y.
|關鍵字:||phase-locked loop;phase synchronization;clock and data recovery;phase;detector;frequency detector;locked loop||Project:||Ieice Transactions on Electronics||期刊/報告no：:||Ieice Transactions on Electronics, Volume E89C, Issue 6, Page(s) 746-752.||摘要:||
A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Retum-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-mu m N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the supply 3 V.
|Appears in Collections:||電機工程學系所|
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