Please use this identifier to cite or link to this item:
標題: Fabrication the Nanodevices by Scanning Probe Lithography and Analying Their Properties (II)
作者: 許薰丰
關鍵字: 掃描探針微影術;Scanning probe lithography;材料科技;矽化物;奈米線;異質結構;奈米電子元件;電性量測;商品化;silicide;nanowires;heterostructures;nano-electric device;electric characteristics measurement
With the shrinking of the dimensions of integrated devices, the exploitation of nano-devices is an important subject for the semiconductor industry. Low-resistivity metal silicides are used as Ohmic contacts, gate electrode, and interconnectors in the semiconductor devices. When the diameter of silicides shrinks to nanosize, the resistivity of silicides is change. In recent years, the nanostructures with the building blocks of silicon nanowires have been widely investigated for both scientific and technological interest. Axial nanowire heterostructure is a candidate for the application of nano-electronic devices.In this project, the silicon nanowires will be fabricated by the scanning probe lithography (SPL) on Silicon-on-Insulator (SOI) substrates. (1) Metal silicide nanowires will be formed by metal deposition and annealing or reactive deposition epitaxy (RDE) process, and their properties of electric conductivity will be measured. (2) Silicon/silicide contacts in nano-size will be fabricated, and their properties of electrical contacts will be measured. (3) Silicide/silcon/silicide nanowire heterostructures will be fabricated by lateral diffusion process, and the properties of carrier transmission in silicon channel will be measured. Additionally, the effect of interlayer on the formation and characteristic of Ni-silicide nanostructures will be studied.We will focus on the effects of the size of nanostructures on the properties of electric conductivity, electrical contact and carrier transmission for the nanowires, silicon/silicide contacts and silicide/silicon/silicide nanowire heterostructures respectively. These results will provide useful information in the development of nano-electric devices.

隨著元件尺寸進入奈米等級,新世代奈米元件的開發,成為半導體產業上的重要課題。在半導體元件中,低電阻率金屬矽化物應用於金屬接觸、閘電極或元件間連線,其導電性質在奈米尺度下的變化,影響它在奈米電子元件的應用性。近來,以矽奈米線為構成元素之奈米結構受到廣泛的研究,其中軸向之奈米線異質結構,為最有潛力發展成為奈米電子元件之結構。本計劃將利用「掃描探微影術(scanning probe lithography)」在絶緣層上覆矽(silicon on insulator,SOI)基材表面製作矽奈米線,進一步(1)嘗試不同的金屬蒸鍍方式,達到製備高品質低電阻率金屬矽化物奈米線,並量測導電性質。(2)發展製備矽/矽化物奈米尺度接觸面之技術,量測接觸性質。(3)發展製備矽化物/矽/矽化物奈米線異質結構之技術,量測電晶體傳輸性質。(4)增加中間層探討其對矽化物奈米結構性質的影響。並深入探討尺寸效應對上述導電性質、接觸性質及電晶體傳輸性質的影響。相關的研究成果將對於發展新世代奈米元件提供重要的參考依據。
其他識別: NSC99-2221-E005-102
Appears in Collections:材料科學與工程學系

Show full item record

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.