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標題: 以四點彎距實驗方法探討無鉛銲錫薄膜試片介金屬擴散成形與孔洞與應力之關聯
Using Four Point Bending Experiment to Study Stress Effects on Lead Free Solder Interfacial IMC Layer Growth and Void Formation
作者: 林明澤
關鍵字: 應用研究;機械工程類
The microelectronics industry has grown rapidly in recent years. The roadmap forsemiconductors plans for developing the complexity and packing density of semiconductordevices into the future allowing ever smaller in the range of nanometer scale and moredensely packed structures to be fabricated. Continued growth of computing power requiresstill further miniaturization, with a corresponding need to understand how length scales affectmechanical behavior in all of its components, especially in its interconnects and packages.In microelectronics packages, the fabrication of a reliable solder joint plays a veryimportant role. Not only in the overall performance of the interconnects, but also thereliability of final device packages. Usually, a good microelectronics package depends on theformation of an intermetallic compound at an interface between the solder and platingmaterial such as Cu, Ag, Ni or Au. Despite the suspected brittle nature of these Sn-basedcompounds, the growth of several microns of an intermetallic is considered a goodmetallurgical bond and good wetting.As the miniaturization in electronics packaging continues, the overall dimension ofsolder interconnects approach the length scale of microstructural features within the joint.Intermetallic compounds comprise an increased volume fraction in these new solder joints ofreduced dimensions and potentially play a greater role in defining the overall mechanicalbehavior of the interconnects. Certain mechanical defects such as Kirkendal void or Whiskerneedle could cause serious problems in interconnect soldering.Recently, the microelectronics industry faces an environmental demand for increasedusage of Pb-free solders. Many of the leading solder alloy candidates for replacement ofPb-Sn solders are based on the Sn-Ag-Cu system. Besides major concerns for solderabilityand manufacturability using these Pb-free alloys, there also exists a need for basicunderstanding of reliability issues such as microstructural evolution of a joint with time andtemperature and most importantly, mechanical stress effects of as-prepared and aged joints.Because of the rapid formation of intermetallics between Sn and many common basis metals,it is expected that the stress effects of Sn-based intermetallics will play a significant role indetermining the reliability in Pb-free soldering.In order to obtain much more accurate stress effect data on the effect of stress state oninterfacial IMC layer growth behavior, the Principal Investigator proposes to conduct anextensive set of experiments on silicon strips using novel design four point bend loadingapparatus. Enhancements to the experimental procedures have considerably improved thequality of the experimental data obtained from the loading experiments and, among otherthings, have allowed us to elucidate much more clearly the relative effect of tensile andcompressive bending to probe the direct link between mechanical stress and interfacial IMClayer growth behavior of solder thin films. Thus can measure the materials properties ofintermetallics compounds commonly formed in reactions of Sn-Ag-Cu solder with Cumetallizations resulted in the formation of intermetallics of interest with a similar length scaleas those formed in electronic joints. This technique has allowed testing of the intermetallics atthe desired length scales and also maintained consistent preparation and experimentalprocedures.Successful completion of this project will provide a uniform database of lead freeSn-based intermetallics, in terms of deformation mechanisms and reliability concerns forbrittle phases in solder joints. These will then be used for the key factors of thin Pb-freesolders film materials use for microelectronics package technologies.

微機電、半導體技術產業近年來已在國內外迅速的成長,且產值超越許多其它產業;為研究及發展更新更快之微機電、半導體元件,學者專家們不斷的增加其複雜性及高密度性(更小尺度的材料和更緊密的架構)。今日電子運算能力能不斷增加的理由就是因為在半導體元件大小方面的縮減,以使更多的元件能被安置在一個微處理器的架構中;也因此,昨天半導體元件範圍在一到數十微米等級寬度的,今天已發展成十到數百奈米的寬度。在持續增加其計算能力的研究上,仍需要更進一步的微型化,但因微小化影響材料結構之機械行為的研究相對也值得重視;其中、在後製程中的導線銲接及封裝技術對封裝及銲接材料受機械應力影響的了解尤為重要。在微封裝技術上,研究及發展出一可靠的導線銲接材料扮演著極為重要的角色,不僅對元件總體功能的穩定性,以及生產製造的可靠度都有著決定性的影響;一般而言,良好的微封裝銲接技術在於能對導線與底板之間產生良好的連結,而此連結是利用銲接材料與欲連接之導線與底板間形成一連接之金屬化合物的界面;目前研究之技術是利用銲錫與包括銅、銀、鎳或金的材料導線或底板來連結。儘管以這些基於錫(Sn)化合物的材料本身的脆性滿高,然一般在欲連接之導線與底板間鍍上數微米的銲錫化合物仍被認為是較好的金屬化合鍵結、亦廣為運用。隨著半導體技術微型化趨勢、整體元件的架構愈形縮小,而相對的在封裝的技術上,對銲接銲料的外形尺寸及相互連接之連結尺度及微結構等也都必須減小使能相容於有限的尺度中;也因此對於因尺度減小產生之尺度效應,即對銲接頭連接區因降低尺度對其機械行為的分析;尤其對其金屬化合物之連接強度、受熱產生殘餘應力對結構內部產生之影響行為例如孔洞(Kirkendall void)尖點(Whisker)等皆顯得重要且亟需了解。最近,由於全球環境對無鉛化的需求、微電子封裝技術產業同樣面對增加無鉛銲料取代既有錫鉛合金的趨勢。而一般在錫鉛銲料的替換原料上,主要所需之銲料合金是建構於銅錫合金Sn-Cu 或是銅銀錫Sn-Cu-Ag 之合金系統。使用這些無鉛的合金在選取及製程上的主要的考量因素除了在銲接接合度solderability 和可合成性manufacturability 外, 也存在對微結構因製程或銲接過程中微結構演化microstructural evolution 的基本理解以及對機械強度的量測,此外隨著時間、溫度、及應力對結構性質的影響與改變亦亟需了解。由於在和接過程中錫與許多基礎金屬之間的intermetallics 的迅速的形成,對於預測錫合金intermetallics 的特性以確定無鉛銲錫銲接後的可靠性分析有著極為重要的價值。本計畫使用四點彎距的應力量測試驗技術,是以計畫主持人以之前設計執行之研究計畫,發展衍伸之以直接的外加應力實驗量測對運用標準製程產生之的無鉛銲錫薄膜成型與擴散之影響。試件製程實驗設計模擬微系統實際製程上銲料的反應與連接環境的狀況,使得研究測試之數據,能清楚對照微封裝製程使用的銲接薄膜材料,於應用過程中產生之材料受機械應力產生之行為特性及使用的相關性,並對其作推論。成功的完成這項研究計畫,將產生完整的數據,對目前研究之各種不同配方之無鉛銲錫薄膜材料可靠性和各項實驗機械應力影響作分析。這些數據將可提供微系統設計製造時選用之無鉛銲錫薄膜材料的之參考,也對產品元件使用之可靠度分析提供一極有價值之研究。
其他識別: NSC98-2221-E005-011
Appears in Collections:精密工程研究所

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