Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/4863
標題: 基於分割轉移矩陣之低功率雙路徑低密度同位元查核碼解碼器設計
Design of Low Power Dual-Path PS-LDPC Decoder
作者: 王泓人
Wang, Hong-Ren
關鍵字: error control code;錯誤更正碼;LDPC code;低密度同位檢查碼
出版社: 通訊工程研究所
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摘要: 
本論文提出了一個基於分割轉移矩陣之低功率/高產出之雙路徑低密度同位元查核碼解碼器設計,使用矩陣大小為512×1024,行權重及列權重分別為3與6之規則建構查核矩陣,在硬體架構上分成四個單元,分別為:變數點單元、查核點單元與兩個訊息儲存單元,訊息儲存單元利用移為暫存器與多工器架構而成。查核點單元以Min-Sum演算法來做為硬體設計原則。
解碼器架構使用特別設計的PS-LDPC編碼,以配合部份平行化之硬體設計。為了減少解多工器與電路繞線所造成的時間延遲問題,我們搭配新建構的查核矩陣與資料重排排序技術,可以去除解多工器與暫存器,可用移位暫存器取代。經由此方法,除了減少硬體需求,也大幅減少繞線複雜度與功率消耗。在傳輸速度方面,由於傳統的解碼方式進行解碼時,變數點單元及查核點單元並非同時運作,因此分別有一半的時間沒有作用,利用適當的編排讓這一半的空閒的時間來進行解碼,如此可讓傳輸速度提升至原本設計的兩倍。
使用TSMC 0.18μm CMOS技術實作後,固定解碼次數8次,在最高工作頻率100MHz時所提出的架構可以達到解碼速率2.844Gbps。實作後完整的低密度同位元檢查碼解碼器晶片面積為10.80mm^2,核心面積為5.18mm^2,在電壓供應1.62伏特時平均功率消耗為571.5mW。

In this thesis, a design of low power high throughput dual-path PS-LDPC decoder is presented. The (512, 1024) check matrix is a regular matrix whose column weight and row weight are 3 and 6, respectively. There are four units including a variable node unit (VNU), a check node unit (CNU), and two message storage units. The message storage unit is composed of shift registers and multiplexers. The min-sum algorithm was applied in the CNU.
With the specially designed PS-LDPC code, the proposed partial parallel architecture using shift registers instead of demultiplexers and registers for message storage can reduce the hardware cost, routing congestion and critical path delay, which resulting lower power consumption. During decoding process of the traditional decoding method, CNU and VNU operations are active alternatively in every decoding iteration. To increase the throughput, these idled CNU and VNU circuit blocks can be utilized more efficiently by the dual-path data flow approach. Therefore, the throughout is increased to almost two times.
After implemented with TSMC 0.18μm CMOS process, the proposed decoder can achieve the decoding throughput of 2.844Gbps at the clock frequency of 100MHz. The chip size is 10.80mm^2, the core size is 5.18mm^2 and the average power consumption with the supply voltage of 1.62V is 571.5mW.
URI: http://hdl.handle.net/11455/4863
其他識別: U0005-1707200917155600
Appears in Collections:通訊工程研究所

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