Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/48960
標題: 以類比三角至正弦轉換技巧設計高速直接式數位頻率合成器(I)
Design of High-Speed Direct Digital Frequency Synthesizers Using Analog Triangular-to-Sinusoid Conversion(I)
作者: 楊清淵
關鍵字: frequency synthesis;頻率合成;電子電機工程類;direct digital frequency synthesizer;digital-to-analogconverter;triangular-to-sinusoid converter;translinear loop;nonlinear operation;resolution;直接式數位頻率合成器;數位類比轉換器;三角至正弦轉換器;轉換線性迴路;非線性;解析度;應用研究
摘要: 
The goal of the research project described in this work is to realize a fully integratedone-chip direct digital frequency synthesizer (DDFS) to be used in high-speed widebandcommunications. This work is devoted to the subject of BiCMOS and CMOS DDFS designsfor future wideband 5-GHz and above 10-GHz applications. Unlike the conventionalROM-based DDFS with a complicated digital processor and the ROM-less DDFS with anonlinear digital-to-analog converter (DAC), the proposed DDFS uses a simple digital phaseaccumulator and linear DAC by employing an analog triangular-to-sinusoid conversion(TSC) technique. The proposed structure has the advantages on high-speed operation, lowpower dissipation and small chip area.There are three main parts in this work: high-speed digital phase accumulator design,high-speed high-resolution DAC design and high-performance TSC design. The phaseaccumulator use a modulator, a pipelined structure built from adder-accumulator blocks andregister blocks. In order to achieve high-speed operation, the digital circuits are implementedby the ECL-like full-differential topology to minimize the propagation delay through thecarry signal path. Adopting a dual-segment structure, the DAC uses a current-steeringarchitecture for high-speed operation and the most significant bits of offset are unaryencoded to reduce glitches while the least significant bits are designed by the binarytopology for simple and high-speed considerations. Two TSC circuits are considered: one isdesigned by bipolar circuit and the other is designed by CMOS circuit. Using the translinearloop technique, the TSC can employ the characteristics of bipolar transistors to provide anapproximate transfer function of triangular-to-sinusoid waveforms. The simulatedperformance of output can reach to the resolution between 8 and 9 bits. Besides, thenonlinear transfer characteristics of the MOS differential pair can also provideapproximately triangular-to-sinusoid transformation. In this projects, the DDFS's will bedesigned to achieve 5-GHz operation with a 8-bit DAC at a 3.3-V 0.35-m BiCMOS, 5-GHzoperation with a 9-bit DAC at a 1.8-V 0.18-m CMOS, and 10-GHz operation with a 8-bitDAC at a 1.2-V 90-nm CMOS, respectively. In response to these designs, there is acontinued search for architectures and circuit techniques enabling a monolithic solution tomeet the more advanced specifications with reasonable chip area and power dissipation.

此研究計畫的目的是要設計一個完全積體化的直接式數位頻率合成器,可以使用於高速寬頻的通信系統。研究以BiCMOS 和CMOS 為技術主軸,開發和設計直接式數位頻率合成器,速度達5 GHz 和10 GHz 以上之應用。不同於傳統使用以ROM 為基礎的直接式數位頻率合成器需要複雜運算的數位處理器以及無ROM 方式的直接式數位頻率合成器需要非線性的數位類比轉換器,我們提出新型直接式數位頻率合成架構,採用類比的三角至正弦波轉換技術,只需電路簡單的數位相位累加器和一個線性的數位類比轉換器;此架構具有高速工作、低功率消耗和小面積設計的優點。電路研究重點主要分三部份:高速數位相位累加器之設計、高頻高解析度數位類比轉換器之設計和高性能三角至正弦轉換器之設計。相位累加器為一種調變器,所用的累加器和記憶體是以導管式架構設計;為了達高速操作,數位電路都是採似ECL 全差動結構之技巧來設計,以減少其延遲時間。數位類比轉換器採用兩段式架構,以電流式扼流電路設計以達高速目的,其中較大位元組的電路以採單一元素設計以降低輸出的突波發生,而較小位元組部份則採二進至方式設計,電路簡單且速度快。至於三角至正弦轉換電路,則分別採用雙載子元件(BJT)和金氧半元件(MOS)設計。利用轉換線性迴路(translinear loop)技巧,我們以雙載子元件設計一種將三角轉換成近似正弦函數的電路,經由模擬分析可達八、九位元的解析特性。其次,藉由金氧半元件的差動對電路的非線性轉換特性,我們將它運用於三角至正弦的轉換,也可得到很好的特性。此計畫中,我們將分別以3.3-V 0.35-m BiCMOS 設計具有八位元數位類比轉換器之5GHz 直接式數位頻率合成器、1.8-V 0.18-m CMOS 設計具有九位元數位類比轉換器之5 GHz 直接式數位頻率合成器以及1.2-V 90-nm CMOS 設計具有八位元數位類比轉換器之10 GHz 直接式數位頻率合成器。對應到這些設計,仍存在著很多的架構和電路技術用來實現單晶片的解決之道,同時也具備著合理的晶片面積和消耗功率以符合我們追求更高電路規格之需求。
URI: http://hdl.handle.net/11455/48960
其他識別: NSC98-2221-E005-077
Appears in Collections:電機工程學系所

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