Please use this identifier to cite or link to this item:
標題: Chip Design of Clock Generation and Frequency Synthesis for Hybrid Optical Fiber Communication Systems
作者: 楊清淵
關鍵字: 應用研究;OFDM;電子電機工程類;optical fiber receiver;radio over fiber;phase-locked loop;clock generator;RF frequency synthesizer
The goal of the research project described in this work is to realize fully integrated clockgeneration and RF frequency synthesis circuits to be used in a low-cost OFDM optical andradio-over-fiber (RoF) receiver. This work is devoted to the subject of CMOS phase-lockedloop (PLL) design for future wideband hybrid optical fiber applications. The PLL is used togenerate a clock signal of the 6-bit ADC with sampling approaching 4 GS/s, and provide LOsignals of 60-GHz RF front ends. There are two main parts in this work: a high-resolutionDS-modulated PLL for 4-GHz clock generation and a high-frequency PLL frequencysynthesizer for 60-GHz RF. Since a frequency and phase offset exists in the received dataand the local clock signal, frequency-offset cancellation is required. A 16-bit DS modulationtechnique is introduced into the PLL. In this way the PLL can perform high resolutionfunction for frequency tuning and phase alignment. Constructed by digital technology, theDS modulator is easy to be integrated and implemented. The calibrated range in this workcan achieve into more than 20 ppm. In 60-GHz RF receiver, the LO frequency planning isdependent on the front-end structure and the LO circuit is also designed by the PLL.Employing a two-stage heterodyne architecture can require a 48-GHz LO as the first stageand a 12-GHz LO in quadrature as the second stage. In the PLLs, an oscillator based on theresonance of an LC-tank is the only one that gives a sufficiently high output frequency witha low noise. The fully integrated VCO with spiral inductors has been implemented instandard CMOS processes. The high-frequency building block is combined together with theother parts of a PLL, such as the divider, the phase detector, the charge pump, and thelow-pass filter, in a charge pump PLL frequency synthesizer that aims at thehigh-performance applications. In addition, since the VCO of the 60GHz RF PLLsynthesizer is based on narrow-band regimes, the narrow-band analog frequency doublermay be more suitable for the first-stage LO to reduce power consumption, increasemaximum operation frequency and remove the high-order harmonics. Moreover, introducingthe frequency doubling regime in the synthesizer can mitigate the speed limitation of theVCO and the divider. In response to these designs, there is a continued search forarchitectures and circuit techniques enabling a monolithic solution to meet our specificationswith reasonable chip area and power dissipation.

此研究計畫的目的是要設計一個完全積體化的時脈產生和頻率合成電路,可以使用於低成本的OFDM 光纖和光載射頻接收器的應用上面。研究主軸是以CMOS 技術設計鎖相迴路電路,應用於寬頻混合光纖通訊系統。我們利用鎖相迴路實現4GHz 時脈信號產生,提供給六位元類比數位轉換器為取樣信號的時脈,以及提供60GHz 射頻前端電路的本地振盪信號。電路研究重點主要分兩部份:高解析度積分三角調變鎖相迴路之時脈產生設計和60GHz 射頻前端本地振盪之頻率合成設計。首先,由於接收的資料率和本地的時脈頻率會有誤差發生,頻率誤差和相位偏移的校正技術是需要的。我們將16 位元三角積分調變技術引進鎖相迴路,使其可達高解析度的頻率和相位調整功能,由於是數位電路,因而易於整合和實現,其校正範圍可達20ppm 以上。其次,對於60GHz 射頻接收器,本地振盪頻率決定於所採用的射頻前端架構,本地振盪電路也是都由鎖相迴路設計。本計畫採用二級外差式架構,需要本地振盪頻率是48GHz 為第一級和12GHz 正交為第二級。就鎖相迴路而言,其振盪器之設計是以電感—電容共振為架構,它是唯一具有高頻率且低雜訊的線路。這種以標準金氧半製程設計了高頻電壓控制振盪器,它是採用螺線型電感設計。結合鎖相迴路的其它元件,如除頻器、相位比較器、充電泵以及低通濾波器,設計出一個充電泵鎖相迴路頻率合成器,目標是要達到高效能上的要求。此外,由於60GHz 射頻應用的鎖相迴路之電壓控制振盪器是屬於窄頻,相對應的窄頻類比二倍頻器則可應用於此第一級的本地振盪,這樣可降低消耗功率、增加工作頻率空間並濾除高階諧波;再者,加入二倍頻於頻率合成輸出,可以減緩振盪器和除頻器等工作頻率的限制。對應到這些設計,仍存在著很多的架構和電路技術用來實現單晶片的解決之道,同時也具備著合理的晶片面積和消耗功率以符合我們的規格之需求。
其他識別: NSC100-2221-E005-040
Appears in Collections:電機工程學系所

Show full item record

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.