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標題: 新穎 3D IC 穿矽孔電鍍銅配方之研發
Research and Development of Novel Copper Electroplating Formulas for through Silicon Vias of 3D IC
作者: 竇維平
關鍵字: 化學工程類;應用研究
在過去的 30 年當中,半導體整合技術已經在2 度空間(2D)構裝中廣泛的應用。這樣的技術不但是在電子工業上被廣泛地應用,也在許多相關工業領域上被廣泛地應用,如光電產業、生物機電產業、生醫系統、電子分析、電腦系統、軍事系統、衛星系統、潛艇系統等。從消費性電子到尖端科技產品以及軍事用途上,幾乎所有的工業產品都結合了半導體元件。半導體製程至所以可以如此快速的進展,主要原因之一是MOS 元件具有良好的可尺寸化能力。但是,材料的尺寸是有限的。目前製程能力已經使用銅內連結技術,到達22 奈米。因此,MOS 元件的發展可能將無法再遵守Moore 定律,因為Moore 定律是基於IC 晶片二度空間封裝的考量。為了落實超大型積體電路(VLSI)晶片的高性能,同時還必須限制其電力的消耗,有兩個方式可以進行。一是由電力消耗的觀點,重新考慮線路與系統的架構;另一個方式則是去建構三度空間(3D)的VLSI 結構。在最近的發展的元件當中發現,信號傳遞延遲主要是由線路長度以及引腳電流容量所主導。而3D-VLSI 的結構設計正好可以在不增加電力消耗的條件之下,解決此問題,同時可以大幅提昇元件性能。關鍵性3D-VLSI 的爭議是訊息的傳遞方式與堆疊晶片之間的電力供給,對於此爭議,有許多方法可以來讓晶片互連,例如藉由打線、邊緣連結、電容或電桿結合以及利用穿矽孔(TSV)直接接通等。根據最近的報導,TSV 似乎是很好的候選者,用來解決多功能、高記憶容量以及低耗電量等的需求。這個製程技術需要絕對專業的電化學沈積(ECD)技巧,因此,在此計畫中,吾人提出四個專業的ECD 技術,包含四個特定的電鍍銅配方,這些配方都可以滿足目前TSV金屬化的需求。這四個ECD 銅配方可以快速修補TSV 側壁上的晶種層;可以產生平面式的孔底上移填充TSV 機制;可以做高度選擇性的填銅以及可以直接填充穿矽通孔(TSH)。一旦這些ECD 銅技術開發成功,TSV 製程的步驟、成本都可以大幅地降低。本計畫預計花三年的時間來開發,其中會用到電化學分析技術、臨場電化學掃描穿隧顯微鏡、電極動力學、電鍍銅配方開發技術以及TSV 製程技術,對於3D IC 的TSV 銅金屬化製程而言,是相當完整的一套研發計畫。

Semiconductor integration technology has been widely spread in two-dimensional applicationsover the past three decades. This wide application has been employed not only in the field of theelectronics industries but also in a lot of related industries such as optoelectronics, bioelectronics,medical systems, electronics analysis, computer systems, military systems, satellite systems,submarine systems, and so on. From the consumer area to ultra-high-end products and militaryusage, almost all industrial products incorporate semiconductor devices. One significant reason forthis rapid progress is the good scalability of metal-oxide-semiconductor (MOS) devices. However,the scale of materials is limited. Right now, the process capability has arrived at 22 nm using copperinterconnects. Therefore, the development of MOS devices may not follow the Moore law, becausethe Moore law is based on the consideration of 2-dimensional packaging of IC chip.In order to bring out high performance from VLSI chips while restricting their powerconsumption, there are two approaches. One is to reconsider circuits and system architecture fromview point of power consumption. Another is to construct three-dimensional VLSI structure. Inrecent devices, the signal propagation delay is mainly determined by wiring length and pincapacitance. Three-dimensional very large-scale integration (3D-VLSI) is the one solution toimprove performance without increase of power consumption. One of the key issues to realize3D-VLSI is the method of information transfer and the supply of electric power among stackedchips. There are many methods to connect interchip, such as wire-bonding, edge connect, capacitiveor inductive coupling method, and direct contact using through-silicon via (TSV).According to the current reports, TSV seems to be a good candidate to solve the requirement ofmultifunction, high memory capacity, low power consumption and so on. This process technologyneeds absolutely professional electrochemical deposition (ECD) technique. In this work, wepropose four professional ECD techniques, including four specific copper plating formulas, whichcan meet the current demand for TSV metallization. These four copper ECD formulas can result inrapid repair of seed layer coated on the sidewall of TSV, bottom-up filling of TSV in a flat planemode, highly selective copper fill, and in direct filling of through silicon hole (TSH). Once thesecopper ECD techniques are successfully developed, the steps and cost of the TSV process can besignificantly reduced. This plan will take three years to come true, in which electrochemicalanalyses, in situ electrochemical scanning tunneling microscopy (EC-STM), electrode kinetics,formulation of copper plating, and processes development of TSV will be employed in this plan.Therefore, this is a complete plan regarding the TSV copper metallization of 3D IC.
其他識別: NSC99-2221-E005-096
Appears in Collections:化學工程學系所

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