Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6013
標題: 高速類比數位轉換器之設計
Design of High-Speed CMOS Flash Analog-to-Digital Converter
作者: 邱韋達
關鍵字: flash;快閃式;ADC;comparator;preamplifier;S/H;類比數位轉換器;比較器;前置放大器;取樣保持電路
出版社: 電機工程學系
摘要: 
類比數位轉換技術是現今積體電路中不可忽視的一環,特別是在資料的傳輸,一個快速精確的A/D轉換器將可大大的減少前級和數位電路的規格要求,本論文中利用差動快閃式的架構設計一個6位元、取樣頻率為500MHz以上的類比數位轉換器,可偵測最小電壓差為20毫伏。為了完成高速和正確的要求,我們使用了分佈式的取樣保持電路、前置放大器和平均的技巧來改善非線性因素對於電路的影響,電位解碼電路來抑制錯誤的發生。此快閃式類比數位轉換器的實現是利用台積電CMOS 0.35μm、1P4M製程來設計,由HSPICE的模擬結果顯示,整個電路在3.3V的電源供應及833MHz的取樣頻率下,有著700mW的功率消耗

The analog-to-digital conversion technique plays an important role in recent develop of integrated circuits, especially in data transmission circuits. A high-speed and precise A/D converter in systems can decrease the required specifications of the front-end and digital portion. This thesis describes the design of a 6-bit, differential and over 500MHz sampling rate A/D converter, which can sense 20mV voltage difference. In order to achieve high-speed and precise objective, we used the distributed S/H, preamplfier and the average technique to improve the relative non-linearity. In addition, the digital encoder is used to suppress the error rate. The flash A/D converter is designed using the in TSMC 0.35μm, 1P4M CMOS technology. HSPICE simulation results show that the A/D converter dissipates 700mW at 833MHz of sampling rate with 3.3V power supply.
URI: http://hdl.handle.net/11455/6013
Appears in Collections:電機工程學系所

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