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Design and Implementation of CCK Demodulator、Timing Recovery and Rake for Wireless LAN IEEE 802.11b
|作者:||黃志豪||關鍵字:||Wireless LAN;無線區域網路;IEEE 802.11b;CCK Demodulator;Timing Recovery;Rake;IEEE 802.11b;互補碼解調變;時序回復;Rake||出版社:||電機工程學系||摘要:||
近年來隨著科技的進步，資料的傳輸方式，已由有線通訊傳輸，進入無線通訊領域，許多無線通訊系統路陸續被提出，無線區域網路IEEE 802.11便是其中之一。IEEE 802.11剛提出時，其資料傳輸速率為1Mbps與2Mbps，由於無線通訊系統以進入多媒體傳送，1Mbps與2Mbps以不能滿足所需，無線區域網路另一傳輸系統被提出，稱之IEEE 802.11b，其資料傳輸速率為5.5Mbps與11Mbps。由於IEEE 802.11b系統資料傳輸速率的提高，相對地，通道中雜訊、干擾與多路徑等效應將變的相當明顯，導致訊號不易辯識，訊雜比因此降低。
In recent years, the way of the data transmission has been upgraded to the wireless communication with technology progress. Many wireless communication systems have been proposed, as the Wireless LAN IEEE 802.11.The data rates of the IEEE 802.11 were 1Mbps and 2Mbps in first, since the data transmission of the Wireless communication is the multimedia transmission now, so the data rates about 1Mbps and 2Mbps are not enough. A new communication system about the IEEE 802.11b was proposed, the data rates of the IEEE 802.11b were 5.5Mbps and 11Mbps. Since the data rate of the IEEE 802.11b was improved, the effect of the channel as noise, interference and mutipath will be obvious. The signal will be indistinct, and the SNR will be reduced.
The study of this thesis is to analyse and simulate the design of receiver baseband circuits of the wireless LAN IEEE 802.11b as Timing Recovery circuit, Rake circuit and a new CCK Demodulator circuit by Verilog and Matlab. Timing Recovery circuit is import for the running of the receiver circuit correctly, and provides the clock of other circuit by the recovery form the perfect correlation of Barker Code. Rake circuit is constructed from the Channel Estimator and the Channel Matched Filter. To base on the detected station of the channel by the Channel Estimator, the signal was composed perfectly by the Channel Matched Filter. A new structure of CCK Demodulator was proposed. It was the better in hardwave implementation than the Fast Walsh Block structure. By the simulator of the optimization of the design analysis in Synopsys, the request for hard implementation of the new structure of CCK Demodulator was 0.53 times of the request of the Fast Walsh Block structure, and their time Delay were approximate.
|Appears in Collections:||電機工程學系所|
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