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Design of a Clock-Deskew Buffer Circuit for Chip-to-Chip Links
|關鍵字:||clock-deskew buffer;時脈誤差校正緩衝器;bidirectional buffer;delay-locked loop;low-voltage differential signaling (LVDS) transmitter;雙向傳輸緩衝器;延遲鎖定迴路;低電壓差動訊號傳輸器||出版社:||電機工程學系所||引用:||“3DIC & TSV Report：Cost, Technologies & Markets,”Yole Development,http://yole.fr/pagesAn/products/Report_sample/3DIC.pdf, Nov.2007. Y. Lee, N. C. Cheng, C. Y. Yang, J. J. Chen and Y. H. Chu,“Method and Apparatus for Clock Skew Compensation,” Industrial Technology Research Institute(ITRI), Sep. 2010. A. H. Atrash, “Data Bus Deskewing System in Digital CMOS Technology,” Ph.D. Dissertation, Georgia Institute of Technology, May 2004. J. Y. Chueh, “A Delay Locked Loop Using Modified Binary Search Algorithm,”M.S. thesis, National Taiwan University, June 2001. C. Y. Yang and S. I. Liu, “A one-wire approach for skew-compensating clock distribution based on bidirectional techniques,”IEEE Journal of Solid-State Circuits, vol. 36, pp. 266-272, Feb. 2001. Y. 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Liu, “ A 0.7-2-GHz Self-Calibrated Multiphase Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 41, no. 5, May. 2006. K. C. Kuo and Y. H. Hsu, “A Low Power Multi-band Selector DLL with Wide-Locking Range,” Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on, pp 25-28, June 2008. M. J. Kim and L. S. Kim, ” A 100MHz-to–1GHz Open-Loop ADDLL with Fast Lock-Time for Mobile Applications,” Custom Integrated Circuits Conference (CICC), 2010 IEEE, Sep. 2010.||摘要:||
With the rapid advances in CMOS technology, the demand for highly integrated VLSI circuit has grown exponentially in recent years. As the system frequency is rising, the problem of timing jitter for circuit modules is more serious. It will decrease the speed and the responsibility, if the timing jitter is too high. So in modern high-speed systems, the skew-free distribution of clocks is very critical for synchronous circuits and the clock-skew problem will become a significant subject.
In this thesis, several architectures which may be used to correct clock skew are introduced. A novel clock-deskew buffer with a latch-based dual delay-locked loop (LBD-DLL) technique is proposed to synchronize the clocks for a chip-to-chip system without delay measurements and dummy delay elements. The LBD-DLL can operate in high frequencies by using the low-voltage differential architecture for the interfaced I/Os. Fabricated in TSMC 0.18-um CMOS process, the circuit can provide the output frequency range of 750MHz to 1.5GHz and the chip area is 0.964mm×0.975mm. When the operation frequency is 1.5GHz, the peak-to-peak jitter of the output clock is 8.89ps and total power dissipation is 33mW under a 1.8-V supply voltage.
Furthermore, in order to provide wide operation range, a wide-range clock-deskew buffer is proposed in the second word. The wide-range operation is achieved in multi-band voltage controlled delay line. This chip is also fabricated in TSMC 0.18-um CMOS process. From the simulation results, we can demonstrate that this clock-deskew buffer can operate from 20MHz to 2GHz. When the operation frequency is 2GHz, the peak-to-peak jitter of the output clock is 9.81ps and total power dissipation is 40mW under a 1.8-V supply voltage. The chip area is 1.39mm×1.39mm.
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