Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6133
標題: 應用於汽車雷達高速分數型頻率合成器之設計與實現
Design and Implement of High Speed Fractional Frequency Synthesizer for Automotive Radar
作者: 林佳俊
Lin, Jia-Jiun
關鍵字: phase locked loop;鎖相迴路;frequency synthesizer;phase noise;voltage control oscillator;頻率合成器;相位雜訊;振盪器
出版社: 電機工程學系所
引用: [1]D.B.Lesson,“A simple model of feedback oscillator noise spectrum,”in Proc.IEEE,vol.54,pp.329-330,Feb.1996 [2]J.J.Rreal,A.A.Abidi,“Physical Processes of Phase Noise in Differential LC Oscillators,”IEEE Custom Integrated Circuits Conference,2000 [3]T.H.Lee,A.Hajimiri,“Oscillator Phase Noise:A Tutorial ”IEEE J.Solid-StateCircuits,vol.35,pp.326-336,March 2000 [4]D.Ham,A.Hajimiri,“Cocept and methods in Optimization of Integrated LC VCOs”IEEE J.Solid-State Circuits,vol.36,June 2001 [5] J. Yuan and C. Svensson, “Fast CMOS nonbinary divider and counter,” Electronics Letters, pp. 1222-1223, June 1993. [6] J. Yuan and C. Svensson, “High speen CMOS circuit technique,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989 [7] F. M. Gardner, “Charge-pump phase-lock loop,” IEEE Trans. Comm., vol COM-28, pp. 1849-1858, Nov, 1980. [8] S. Kim et. al, “A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, no. 5, May, 1997. [9] M. Mansuri, D. Liu and C.-K. K. Yang, “Fast Frequency Acquistion Phase-Frequency Detector for GSamples/s Phashe-Locked Loops,” IEEE J. Solid-State Circuits, vol. 37, no. 10, Oct, 2002. [10] Sheng.Chou Lee, Master thesis,National Taiean University,2004 [11]Y.Koo, H.Huh, Y.Cho, J.Lee, J.Park, K.Lee, D.K.Jeong, and W.Kim,“A fully integrated CMOS frequency synthesizer with charge averaging charge pump and dual-path loop filter for PCS and cellular CDMA wireless system”IEEE J.Solid-State Circuit, vol.37, no.5,pp 536-542,May 2002 [12]Tai-Cheng Lee and Behzad Razavi“A Stabilization Technique for Phase-Locked Frequency Synthesizers”IEEE J.Solid-State Circuit, vol.38, no.4 ,June 2003 [13]Hsiang-Hui Chang, I-Hui Hua, Shen-Iuan Liu “A Soead-Spectrum Clock Generator With Triangular Modulation” IEEE J.Solid-State Circuit, vol.38,no.4 ,Aprial 2003 [14]F.M.Gardner, Phase lock Techniques, Second Ed, New York: Wiley & Sons,1979 [15] M.H.Perrott, M.D.Trott, and C.G.Sodini,“A Modeling Approach for Σ-△ Fractional-N Frequency Synthesizer Allowing Straigtforward Noise Analysis”IEEE J.Solid-State Circuit,vol.37,no.8,Aug.2002,pp.1028-1038 [1] Razzavi課本 [2] N.H.W. Fong, J.-O. Plouchart, N. Zamdmer, Duixian Liu, L.F. Wagner, C. Plett and N.G. Tarr, “Design of wide-band CMOS VCO for multiband wireless LAN applications”, IEEE J. Of Solid-State Circuits, Vol. 38, No.8, pp. 1333-1341, Aug. 2003 [3] Zhenbiao Li and Kennethh K. O., “A Low-Phase-Noise and Low-Power Multiband CMOS Voltage-Controlled Oscillator”, IEEE J. Of Solid-State Circuits, Vol. 40, No. 6, JUNE 2005. [4]Pietro Andreani and Seven Mattisson “On the Use of MOS Varactors in RF VCO''s” IEEE J. Of Solid-State Circuits, Vol. 35, No. 6, JUNE 2000 [5] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp.717-724, May 1999. [6] E. Hegazi, H. Sjoland, and A. A. Abidi, “A Filtering Technique to Lower LC Oscillator Phase Noise,” IEEE Journal of Solid State Circuits, vol. 36, no. 12, pp.1921-1930, Dec. 2001 [7] S. Levantino, et. al., “Frequency Dependence on Bias Current in 5-GHz CMOS VCOs: Impact on Tuning Range and Flicker Noise Upconversion,” IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp.1003-1011, Aug. 2002. [8] C. –Y. Kuo, J. –Y. Chang, and S. –I. Liu, “A Spur-Reduction Technique for a 5-GHz Frequency Synthesizer,” IEEE Trans. on Circuits and Systems I, vol. 53, no. 3, pp.526-533, Mar. 2006. [9] T.W.Brown, F.Farthabakhshian, A.G.Roy, T.S.F, K.M “A 475VmV, 4.9GHz Enhanced Swing Differential Colpitts VCO with Phase Noise of -136dBc/Hz at a 3MHz Offset Frequency” IEEE J.Solid-State Circuit,vol 46, No 8, Augst 2011 [10] J.P.Hong, S.G.Lee“Low Phase Noise Gm-Boosted Differential Gate-to-Sourcce Feedback Colpitts CMOS VCO” IEEE J.Solid-State Circuit,vol 44, No 11, November 2009 [11] Hsieh-Hung Hsieh, and Liang-Hung Lu,“A V-Band CMOS VCO With an Admittance-Transforming Cross-Coupled Pair”IEEE J.Solid-State Circuit, Vol.44, No 6, June 2009 [12] P.C.Huang, M.D.Tasi, G.D.Vendelin, H.Wang, C.H.Chen, C.S.Chang “A Low-Power 114-GHz Push-Push CMOS VCO Using LC Source Degeneration”IEEE J.Solid-State Circuit, Vol.42, No.6, June 2007 [13] Chih-Hsiang Chang, Ching Yuan Yang“A 0.18-um CMOS 16-GHz Varactorless LC-VCO with 1.2-GHz Tunning Range”IEEE ASSCC, pp.107-110, November 2007 [14]Kun-Hung Tasi, Shen-Iuan Liu“A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency”IEEE Trans.on VLSI System,vol.20, pp.80-88, Jan.2012 [15] Ching-Yuan Yang, Chih-Hsiang Chang, Jung-Mao Lin, Hsuan-Yu Chang, “A 20/40-GHz Dual-Band Voltage-Controlled Frequency Source in 0.13-μm CMOS,” Transactions on IEEE Microwave Theory and Techniques, vol.59, no.8, pp.2008-2016, August 2011. (SCI、EI) [16] Kun-Hung Tasi, Shen-Iuan Liu“A Millimeter-Wave Phase-Locked Loop Using a Novel Oscillator”IET circuit,Devices & System ,CDS-2010-0091,Mar.2010 [14]D.B.Lesson,“A simple model of feedback oscillator noise spectrum,”in Proc.IEEE,vol.54,pp.329-330,Feb.1996 [15] Ching-Yuan Yang, Chih-Hsiang Chang, “Low Voltage 0.13-um CMOS Voltage-Controlled Oscillator and Frequency Doubler,” Journal of Engineering, National Chung Hsing University, vol.21, no.1, pp.46-53, March 2010. [16] Rofougaran, A., Rael, J., Rofougaran, M. and Abidi, A.A., “A 900 MHz CMOS LC-Oscillator with Quadrature Outputs,” International Solid-Sate Circuits Conference, San Francisco, pp. 392-393 (1996). [17] Gierkink, S.L.J., Levantino, S., Frye, R.C., Samori, C. and Boccuzzi, V., “A Low-Phase- Noise 5-GHz CMOS Quadrature VCO Using Superharmonic Coupling,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, pp. 1148- 1154 (2003). [18]S.Li,I.Kipnis,and M.Ismail,“A 10-GHz CMOS quadrature LC-VCO for multirate optical applications”IEEE J.Solid-State Circuit, Vol.38,pp.1626-1634, Oct.6, June 2007 [19] Kwok, K. and Luong, H.C., “Ultra-Low- Voltage High-Performance CMOS VCOs Using Transformer Feedback,” IEEE Journal of Solid- State Circuits, Vol. 40, No. 3, pp. 652-660 (2005). [20] Chang, C.-H. and Yang, C.-Y., “A Low-Voltage High-Frequency CMOS LC-VCO,” IEEE Radio Frequency Integrated Circuits Symposium, Atlanta, pp. 545-548 (2008). [21] Hsieh, H.-H. and Lu, L.-H., “A High-Performance CMOS Voltage-Controlled Oscillator for Ultra- Low-Voltage Operations,” IEEE Transaction on Microwave Theory and Technique, Vol. 55, No. 3, pp. 467-473 (2007). [1] H. Huh and Y. Koo, “Comparison Frequency Doubling and Charge Pump Matching Techniques for Dual-Band ΔΣ Fractional-N Frequency Synthesizer,” IEEE J. Solid-State Circuits, vol. 40, no. 11, November 2005. [2]Chun-Huat Jeng, Bang-Sup Song,“A 1.8-GHz CMOS Fractional-N Frequency Synthesizer With Randomized Multiphase VCO” IEEE J. Solid-State Circuits, vol. 38, no. 6, June 2003. [3] S. Park, Principle of Sigma-Delta Modulation for Analog-to-Digital Converters, Motorola Available on http://www.numerix-dsp.com/appsnotes/ APR8-sigma-delta.pdf [4] M. H. Perrot, M. D. Trott, and C. G. Sodini, “A modeling approach for Σ-Δ fractional-N frequency synthesizer allowing straightforward noise analysis,” IEEE Journal Solid-State Circuits, vol. 37, no. 8, pp.1028—1038, Aug. 2002. [5] S. Pamarti, L. Jansson, and I. Galton, “A Wideband 2.4GHz Delta-Sigma Fractional-N PLL With 1Mb/s In-Loop Modulation,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 49–62, Jan. 2004. [6] S. E. Meninger and M. H. Perrott, “A 1-MHz Bandwidth 3.6-GHz 0.18-um CMOS Fractional-N Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 966-980, April 2006 [7] Y. –C. Yang, S. –A. Yu, Y. –H. Liu, T. Wang, and S. –S. Lu, “A Quantization Noise Suppression Technique for ΔΣ Fractional-N Frequency Synthesizers,”IEEE Journal of Solid-State Circuits, vol. 41, pp. 2500-2511, Nov. 2006 [8]M.Gupta and B.-S. Song,“A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration”IEEE J.Solid-State Circuit,vol.41,pp2842-2851,Dec.2006 [9]S.E.Meninger,M.H.Perrott,“A 1-MHz bandwidth 3.6-GHz 0.18-um CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise”,IEEE J. Solid-State Circuit, vol.41,pp.966-980,April 2006 [10]W.-H.Chiu, C.-Y.Cheng, and T.H. Lin,“A 5-GH fractional-N phase-locked loop with spur reduction technique in 0.13-um CMOS”IEEE ISCAS, pp.2996-2999,May 2010 [11]C.H. Heng, and B.S. Song,“A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO”IEEE J. Solid-State Circuit, vol.38,pp.845-854, June 2003. [12]M.Zanuo, S.Levantino, C.Samori, and A.L.Lacaita,“A windeband 3.6GHz digital ΔΣfractional-N PLL with phase interpolation divider and digital spur cancellation ”IEEE J. Solid-State Circuit, vol.46,pp.627-638,March 2011 [13]C.-C. Hung and S.-I. Liu,“A noise filtering technique for fractional-N frequency synthesizer”IEEE Trans. on Circuits and Systems II, vol.58,pp.139-143,March 2011 [14]Y.-C. Yang and S.-S. Liu,“A Quantization noise pushing technique for ΔΣ fractional-N frequency synthesizer”IEEE Trans. on Microwave Theory and Techniques, vol.56,pp. 817-825,April 2008 [15]C.-H.Lee, L.-C. Cho, J.-H. Wu, and S.-I. Liu,“A 50.8-53-GHz clock generator using a harmonic-locked PD in 0.13-um CMOS”IEEE Trans. on Circuit and Systems II, vol.55, pp.404-408, May 2008 [1] 台灣車輛研發聯盟/中山科學研究院;www.digitimes.com.tw. [2] J.Craninckx and M.Steyaert, “A 1.75-GH/3-V dual-modulus divide-by-128/129 prescaler in 0.7-um CMOS,” IEEE J.Solid-State Circuit, vol.31 no. 7,pp. 890-897, Jul. 1996 [3] B. Razavi, RF Microelectronics. New Jersey: Prentice Hall, 1998. [4] J.Craninckx and M.Steyaert, “A 1.75-GH/3-V dual-modulus divide-by-128/129 prescaler in 0.7-um CMOS,” IEEE J.Solid-State Circuit, vol.31 no. 7,pp. 890-897, Jul. 1996 [5] S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang, “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp.1039-1045, Jul. 2000 [6] T. Riley, M. Copeland, and T. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553–559, May 1993 [7] Y. –C. Yang, S. –A. Yu, Y. –H. Liu, T. Wang, and S. –S. Lu, “A Quantization Noise Suppression Technique for ΔΣ Fractional-N Frequency Synthesizers,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 2500-2511, Nov. 2006 [8] H. Huh, et al., “A CMOS Dual-Band Fractional-N Synthesizer with ReferenceDoubler and Compensated Charge Pump,” in ISSCC 2004, Section 5.5 [9] J. –S. Lee, “Charge Pump with Perfect Current Matching Characteristics in Phase-Locked Loops,” Electronics Letters, vol. 36, no. 23, pp.1907-1908, Nov. 2000. [10] T.-H. Lin, C.-L. Ti, and Y.-H. Liu, “Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs,” IEEE Trans. Circuits Syst. - I, vol. 56, pp. 877-885, May 2009. [11] W.-H. Chiu, Y.-H. Huang, and T.-H. Lin, “A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 1137-1149, June 2010
摘要: 
隨著製程技術快速發展,同時帶動積體電路操作速度上的突破,成就了微電腦處理器的運算速度大幅提升。在無線通訊系統上,寬頻應用技術以成為當前與未來的潮流,本論文是以高速無線通訊作為研究主題。

首先,介紹一應用於短距離汽車防撞雷達的考畢茲振盪器,它有别於傳統振盪器的振盪頻率與起振條件,論文中將會推導與模擬出,此架構的確可操作在較高的頻率並且易於振盪。
第二,本論文使用了電流重複利用的技巧,來減少功率的消耗,我們延續先前高頻電路上的設計技巧,以及結合電流重複利用的方式,來達到既高速又低功率消耗的振盪源,此電路實現於TSMC 0.18um標準CMOS製程,在1.8V電壓操作下功率消耗為6.7mW,其振盪器在輸出頻率為5GHz下,相位雜訊為-126.96 dBc/Hz@1MHz,其倍頻器在輸出頻率為9.94GHz下,相位雜訊為-118.38 dBc/Hz@1MHz。
最後一部分,本論文提出了高速且具雙模數的預除器,去解決高速頻率合成器所帶來解析度不足的缺點,此架構除了可應用於高速頻率合成器外,在抑制分數型頻率合成器(ΔΣ架構)的量化雜訊,也可預期有相當顯著的成果,在電路實現過程中遇到的Spike問題,此預除器也將一併解決之,此電路在一倍頻與二倍頻輸出,分別為11GHz、22GHz,其相位雜訊在1MHz偏移處為-89.75 dBc/Hz、-106.72 dBc/Hz。在1.8V電壓操作下功率消耗為28mW,晶片面積為1.19 × 1.22 mm2。

With the rapid advances in technology, the operation frequency of the microprocessor is increasing rapidly. In wireless communication system, the wide bandwidth technique proposed future trends.In the thesis we proposed take high-speed wireless communications as the research topic.

First, a Colpitts oscillator which is used to the automotive radar is introduced. Its oscillator frequency and start condition are different from the traditional ones. We derivate and simulate this oscillator to prove that it can operate in high frequency and be easy to oscillate.

The second part describes a current-reused quadrature VCO with a frequency doubler to achieve the high-frequency and low-power characteristics. The crcuit is fabricated in TSMC 0.18um CMOS process, and the power consumption is 6.7mW under a 1.8-V supply voltage. At 1-MHz offset from a 5-GHz carrier of the oscillator and a 9.94-GHz carrier of the frequency multiplier, the measured phase noises are -126.96 dBc/Hz and -118.38 dBc/Hz respectively.

Finally, to solve the problem of insufficient resolution in a high-speed frequency synthesizer, a high-speed and dual-modulus prescaler is presented. This architecture can not only apply to high-speed frequency synthesis but also suppress quantization noise in the delta-sigma modulator based frequency synthesizers. Moreover, the proposed circuit can solve the spike in the prescaler. The chip output frequencies are 11GHz and 22GHz on the main tone and the double tone respectively. The phase noise at 1MHz offset are about -106.72dBc/Hz and -89.75dBc/Hz. It dissipates 28mW with 1.8-V supply, and the total area is 1.19×1.6mm2
URI: http://hdl.handle.net/11455/6133
其他識別: U0005-0406201215070200
Appears in Collections:電機工程學系所

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