Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6133
DC FieldValueLanguage
dc.contributor陳巍仁zh_TW
dc.contributor許恆壽zh_TW
dc.contributor.advisor楊清淵zh_TW
dc.contributor.author林佳俊zh_TW
dc.contributor.authorLin, Jia-Jiunen_US
dc.contributor.other中興大學zh_TW
dc.date2013zh_TW
dc.date.accessioned2014-06-06T06:37:21Z-
dc.date.available2014-06-06T06:37:21Z-
dc.identifierU0005-0406201215070200zh_TW
dc.identifier.citation[1]D.B.Lesson,“A simple model of feedback oscillator noise spectrum,”in Proc.IEEE,vol.54,pp.329-330,Feb.1996 [2]J.J.Rreal,A.A.Abidi,“Physical Processes of Phase Noise in Differential LC Oscillators,”IEEE Custom Integrated Circuits Conference,2000 [3]T.H.Lee,A.Hajimiri,“Oscillator Phase Noise:A Tutorial ”IEEE J.Solid-StateCircuits,vol.35,pp.326-336,March 2000 [4]D.Ham,A.Hajimiri,“Cocept and methods in Optimization of Integrated LC VCOs”IEEE J.Solid-State Circuits,vol.36,June 2001 [5] J. Yuan and C. Svensson, “Fast CMOS nonbinary divider and counter,” Electronics Letters, pp. 1222-1223, June 1993. [6] J. Yuan and C. Svensson, “High speen CMOS circuit technique,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989 [7] F. M. Gardner, “Charge-pump phase-lock loop,” IEEE Trans. Comm., vol COM-28, pp. 1849-1858, Nov, 1980. [8] S. Kim et. al, “A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL,” IEEE J. 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Lin, “A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 1137-1149, June 2010zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/6133-
dc.description.abstract隨著製程技術快速發展,同時帶動積體電路操作速度上的突破,成就了微電腦處理器的運算速度大幅提升。在無線通訊系統上,寬頻應用技術以成為當前與未來的潮流,本論文是以高速無線通訊作為研究主題。 首先,介紹一應用於短距離汽車防撞雷達的考畢茲振盪器,它有别於傳統振盪器的振盪頻率與起振條件,論文中將會推導與模擬出,此架構的確可操作在較高的頻率並且易於振盪。 第二,本論文使用了電流重複利用的技巧,來減少功率的消耗,我們延續先前高頻電路上的設計技巧,以及結合電流重複利用的方式,來達到既高速又低功率消耗的振盪源,此電路實現於TSMC 0.18um標準CMOS製程,在1.8V電壓操作下功率消耗為6.7mW,其振盪器在輸出頻率為5GHz下,相位雜訊為-126.96 dBc/Hz@1MHz,其倍頻器在輸出頻率為9.94GHz下,相位雜訊為-118.38 dBc/Hz@1MHz。 最後一部分,本論文提出了高速且具雙模數的預除器,去解決高速頻率合成器所帶來解析度不足的缺點,此架構除了可應用於高速頻率合成器外,在抑制分數型頻率合成器(ΔΣ架構)的量化雜訊,也可預期有相當顯著的成果,在電路實現過程中遇到的Spike問題,此預除器也將一併解決之,此電路在一倍頻與二倍頻輸出,分別為11GHz、22GHz,其相位雜訊在1MHz偏移處為-89.75 dBc/Hz、-106.72 dBc/Hz。在1.8V電壓操作下功率消耗為28mW,晶片面積為1.19 × 1.22 mm2。zh_TW
dc.description.abstractWith the rapid advances in technology, the operation frequency of the microprocessor is increasing rapidly. In wireless communication system, the wide bandwidth technique proposed future trends.In the thesis we proposed take high-speed wireless communications as the research topic. First, a Colpitts oscillator which is used to the automotive radar is introduced. Its oscillator frequency and start condition are different from the traditional ones. We derivate and simulate this oscillator to prove that it can operate in high frequency and be easy to oscillate. The second part describes a current-reused quadrature VCO with a frequency doubler to achieve the high-frequency and low-power characteristics. The crcuit is fabricated in TSMC 0.18um CMOS process, and the power consumption is 6.7mW under a 1.8-V supply voltage. At 1-MHz offset from a 5-GHz carrier of the oscillator and a 9.94-GHz carrier of the frequency multiplier, the measured phase noises are -126.96 dBc/Hz and -118.38 dBc/Hz respectively. Finally, to solve the problem of insufficient resolution in a high-speed frequency synthesizer, a high-speed and dual-modulus prescaler is presented. This architecture can not only apply to high-speed frequency synthesis but also suppress quantization noise in the delta-sigma modulator based frequency synthesizers. Moreover, the proposed circuit can solve the spike in the prescaler. The chip output frequencies are 11GHz and 22GHz on the main tone and the double tone respectively. The phase noise at 1MHz offset are about -106.72dBc/Hz and -89.75dBc/Hz. It dissipates 28mW with 1.8-V supply, and the total area is 1.19×1.6mm2en_US
dc.description.tableofcontents致謝 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - i 摘要(中文) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ii 摘要(英文) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -iii 目錄 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - iv 第一章 緒論 1.1 研究動機 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -1 1.2 短距離汽車雷達防撞雷達簡介 - - - - - - - - - - - - - -- - - - - - - - - - - - - -2 1.3 論文架構簡介 - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - -3 第二章 鎖相廻路簡介 2.1 鎖相迴路的基本介紹 - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - -4 2.2 特性考量 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -5 2.2.1 相位雜訊分析 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --5 2.2.2 Reference spur - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -12 2.2.3 Settling time - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -14 2.3 鎖相廻路分析 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -15 2.4 相位雜訊分析 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -23 2.4.1 子區塊的雜訊轉移函數 --- - - - - - - - - - - - - - - - - - - - - - - - - - - 24 2.4.2 鎖相廻路頻寬的最佳化 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 25 第三章 壓控振盪器分析與探討 3.1 壓控振盪器操作原理與分析 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 27 3.2 各類壓控振盪器介紹 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 30 3.3 降低起振條件之考畢茲(Colpitts)壓控振盪器 - - - - - - - - - - - - - - - -35 3.3.1 電路模擬 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -39 3.3.2 晶片量測 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -40 3.4 低功耗壓控振盪器 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 44 3.4.1 低電壓壓控振盪器 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -44 3.4.2 電流重複利用壓控振盪器與倍頻--- - - - - - - - - - - - - - - - - - - - - 45 3.4.3 晶片量測 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --48 第四章 分數型頻率合成器 4.1 為何要分數型頻率合成器 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -54 4.2 分數型頻率合成器架構 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----55 4.2.1 三角積分調變器 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 58 4.3 ΔΣ調變器對於頻率合成器的雜訊特性 - - - - - - - - - - - - - - - - - - - --61 4.4 改善量化誤差的各種方法 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -63 4.4.1 誤差補償技巧 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -63 4.4.2 多重相位操作 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -64 4.4.3 量化誤差濾除技巧 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -65 4.4.4 提高調變頻率 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -66 第五章 應用於汽車雷達高速分數型頻率合成器之設計與實現 5.1 簡介 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 69 5.2 系統架構說明與實現 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --70 5.3 頻率合成器量測結果 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 88 第六章 結論與未來展望 6.1 結論 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -95 6.2 未來展望 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -95zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-0406201215070200en_US
dc.subjectphase locked loopen_US
dc.subject鎖相迴路zh_TW
dc.subjectfrequency synthesizeren_US
dc.subjectphase noiseen_US
dc.subjectvoltage control oscillatoren_US
dc.subject頻率合成器zh_TW
dc.subject相位雜訊zh_TW
dc.subject振盪器zh_TW
dc.title應用於汽車雷達高速分數型頻率合成器之設計與實現zh_TW
dc.titleDesign and Implement of High Speed Fractional Frequency Synthesizer for Automotive Radaren_US
dc.typeThesis and Dissertationzh_TW
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.fulltextno fulltext-
item.languageiso639-1en_US-
item.grantfulltextnone-
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