Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6194
標題: 十位元單端輸入之連續逼近暫存式類比數位轉換器使用加權二進位電容結構之佈局研究
The Layout Study of a 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture
作者: 鍾承諭
Chung, Cheng-Yu
關鍵字: 類比數位轉換器;SAR ADC;電容陣列;cap array
出版社: 電機工程學系所
引用: [1] Hao-Chiao Hong, and Guo-Ming Lee, “A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC,” IEEE J. Solid-State Circuits, vol. 42, no. 10, Oct 2007. [2] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, and Ying-Zu Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, Apr 2010. [3] Kuramochi Y.,Matsuzawa A. and Kawabata M., “A 0.05-mm2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS,” IEEE Asian Solid-State Circuits Conf.(ASSCC.), pp. 224 – 227, Jul. 2007. [4] Kazuaki Deguchi, Naoko Suwa, Masao Ito, Toshio Kumamoto, and Takahiro Miki, “A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 10, Oct 2008. [5] .Behzad Razavi, “Principles of Data Conversion System Design,” John Wiley & Sons, Inc., 1995. [6] Andrew M. Abo and Paul R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, May 1999. [7] .Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw Hill, 2001 [8] R.Jacob Baker, “CMOS Circuit Design, Layout, and Simulation,” Published by Wiley-IEEE, 3rd Edition, 2010. [9] .M. Yip, P.Anantha Chandrakasan “A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC,” ISSCC Dig. Tech. Papers, pp. 190 – 192, Feb. 2011. [10] .M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta, “A 1.9uW 4.4fJ/Conversion-step 10b 1MS/s Charge Redistribution ADC,” IEEE ISSCC pp. 244-610 Feb. 2008. [11] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, "A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS,” in IEEE Symp. VLSI Circuits Dig., pp. 241-242, Jun. 2010. [12] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, Chih-Hao Huang, Linkai Bu, Chih-Chung Tsai, "A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation, “ ISSCC Dig. Tech. Papers, pp. 386-387, Feb. 2010. [13] .Masato Yoshioka, Masahiro Kudo, Kunihiko Gotoh, Yuu Watanabe Fujitsu Laboratories, “A 10b 125MS/s 40mW Pipelined ADC in 0.18μm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 282-283, Feb. 2005. [14] .A. Agnes et al., “A 9.4-ENOB 1V 3.8μW l00 kS/s SAR ADC with time-domain comparator,” in IEEE ISSCC Dig. Tech. Papers, pp.246–247, Feb. 2008. [15] Seon-Kyoo Lee, Seung-Jin Park, Hong-June Park, and Jae-Yoon Sim, “A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface,” IEEE J. Solid-State Circuits, vol. 46, no. 3, Mar 2011. [16] 張振豪 “十位元單端輸入之連續逼近暫存式類比數位轉換器使用加 權二進位電容結構” 國立中興大學碩士論文,中華民國一百年七月
摘要: 
本篇論文主要說明一個單端輸入之十位元連續逼近式類比數位轉換器的設計及佈局考量。取樣保持電路使用互補式開關(sar14)及靴帶式開關(sar15)、比較器可達到軌對軌輸入範圍,並以加權二進位電容陣列之架構來實現數位類比轉換之子電路,佈局考量主要是將類比及數位之電源完全分開,避免數位電路產生的雜訊干擾類比電路之穩定。

在TSMC 0.18um Mixed-Signal 1P6M polycide 1.8V製程sar14晶片面積為1.096*1.149 mm2。供應電壓為2V,取樣率為910kS/s,輸入弦波頻率為90kHz時(振幅為0.1V-1.9V),所量測到之訊號雜訊失真比為49.63dB、微分非線性度介於+2.7407/-1.2764LSB、積分非線性度介於+2.0862/-1.0LSB,總功率消耗為1.7mW。

在TSMC 0.18um Mixed-Signal 1P6M polycide 1.8V製程sar15晶片面積為1.096*1.149 mm2,當供應電壓為2V,取樣率為910kS/s,輸入弦波頻率為90kHz時(振幅為0.1V-1.9V),所量測到之訊號雜訊失真比為54.3dB、微分非線性度介於+0.6340/-0.8240LSB、積分非線性度介於+0.9422/-0.8090LSB,總功率消耗為1.7mW。

This thesis focuses on the design and the layout of a 10-bit single ended Successive Approximation Register ADC. A complementary switch(sar14) and a bootstrap switch(sar15) are used for the sample and hold circuit, and the rail to rail input range is for the comparator design. Also, a binary-weighted capacitor architecture is used to achieve sub- circuit digital to analog converter. The layout is mainly set to separate the analog power source from the digital power source in order to keep the stability of analog circuit from interference made by digital circuit.

TSMC 0.18um Mixed-Signal 1P6M polycide 1.8V process produces a chip area -- 1.096*1.149 mm2 with sar15 chip. Measurement results show that at a 2-V supply , 910kS/s, and input frequency of sine wave 91kHz(amplitude is 0.1V~1.9V), the ADC achieves an SNDR of 49.63 dB. DNL is between +2.7407/-1.2764LSB and INL is between +2.0862/-1.0LSB. The power consumption is 1.7mW.

Similarly, TSMC 0.18um Mixed-Signal 1P6M polycide 1.8V process produces a chip area -- 1.096*1.149 mm2 with sar15 chip .Measurement results show that at a 2-V supply , 910kS/s, and input frequency of sine wave 91kHz(amplitude is 0.1V~1.9V), the ADC achieves an SNDR of 54.3 dB. DNL is between +0.6340/-0.8240LSB and INL is between +0.9422/-0.8090LSB. The power consumption is 1.7mW.
URI: http://hdl.handle.net/11455/6194
其他識別: U0005-0602201211343100
Appears in Collections:電機工程學系所

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