Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6204
標題: 十位元單端輸入之連續逼近式類比數位轉換器使用加權二進位電容結構
A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture
作者: 張振豪
Chang, Chen-Hao
關鍵字: ADC;類比數位轉換器;Single End;Binary-weighted;單端;加權二進位
出版社: 電機工程學系所
引用: [1] Hao-Chiao Hong, and Guo-Ming Lee, “A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC,” IEEE J. Solid-State Circuits, vol. 42, no. 10, Oct 2007. [2] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, and Ying-Zu Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, Apr 2010. [3] Kuramochi Y.,Matsuzawa A. and Kawabata M., “A 0.05-mm2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS,” IEEE Asian Solid-State Circuits Conf.(ASSCC.) Jul. 2007, pp. 224 - 227. [4] Kazuaki Deguchi, Naoko Suwa, Masao Ito, Toshio Kumamoto, and Takahiro Miki, “A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 10, Oct 2008. [5] Behzad Razavi, “Principles of Data Conversion System Design,” New York: IEEE Press,1995. [6] Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang and Shen-Iuan Liu, “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 35, no. 8, Aug 2000. [7] R.Jacob Baker, “CMOS Circuit Design, Layout, and Simulation,” IEEE press. [8] Masato Yoshioka, Masahiro Kudo, Kunihiko Gotoh, Yuu Watanabe Fujitsu Laboratories, “A 10b 125MS/s 40mW Pipelined ADC in 0.18μm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 282-283. [9] Naveen Verma, Anantha P. Chandrakasan, “An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes,” IEEE J. Solid-State Circuits, vol. 42, no. 6, Jun 2007. [10] A. Agnes et al., “A 9.4-ENOB 1V 3.8μW l00 kS/s SAR ADC with time-domain comparator,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp.246-247. [11] Seon-Kyoo Lee, Seung-Jin Park, Hong-June Park, and Jae-Yoon Sim, “A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface,” IEEE J. Solid-State Circuits, vol. 46, no. 3, Mar 2011. [12] Andrew M. Abo and Paul R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, May 1999. [13] Brian P. Ginsburg, and Anantha P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, Apr 2007. [14] You-Kuang Chang, Chao-Shiun Wang and Chorng-Kuang Wang, “A 8-bit 500 KS/s low power SAR ADC for bio-medical application,” in IEEE ASSCC Dig. Tech. Papers, Nov. 2007, pp. 228-231. [15] Zhiheng Cao, Shouli Yan and Yunchu Li, “A 32mW1.25 GS/s 6 b 2 b/step SAR ADC in 0.13 μm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp.542-543.
摘要: 
本篇論文描述一個單端輸入之十位元連續逼近式類比數位轉換器的設計,以互補式開關完成取樣保持電路,並設計一個可操作在軌對軌輸入範圍的比較器,數位類比轉位器則是建立在加權二進位電容陣列架構上,並加入一個可對數位類比轉位器輸出節點放電的開關,避免電容陣列殘留多餘的電荷。

實驗結果顯示,在使用台積電0.18微米製程,整個類比數位轉換器的晶片面積為1.032*1.098 mm2,當供應電壓為2V,取樣率為910kS/s,輸入弦波頻率為90kHz時,所量測到之訊號雜訊失真比為52dB、微分非線性度介於+3.02/-1LSB、積分非線性度介於+0.55/-8.52,總功率消耗為1.93mW。
URI: http://hdl.handle.net/11455/6204
其他識別: U0005-0608201116341900
Appears in Collections:電機工程學系所

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