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Implementation and Study of Post Processors for Multi-Rate LDPC Decoders in 16-QAM Radio-Over-Fiber Systems
|關鍵字:||多碼率;16-QAM;低密度同位元查核碼解碼器;無線光纖傳輸;錯誤基數;里德索羅門碼;後處理;Low Density Parity Check;multi-rate;Radio Over Fiber;Layered Min Sum Algorithm;error floor;Reed-Solomon;Check Node Tracing Method;Reduced-Back-Tracking Method;Absorbing set;trapping set;post-processing||出版社:||電機工程學系所||引用:|| R. G. Gallager, “Low density parity check node codes,” IRE Trans. Inf. Theory, vol. IT-8, no.1, pp.21-28,Jan. 1962.  IEEE Draft Standard for Information Technology-Telecommunications and information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements-Part 11: Wireless LAN Medium Amendment : Enhancements for Higher Throughput, Feb. 2007, IEEE Std. 802.11n.  IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems Amendment 2: Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands and Corrigendum 1, Feb. 2006, IEEE Std. 802.16e.  IEEE Standard for Information Technology-Telecommunications and Information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements-Part 3: Carrier Sense Multiple Access With Collision Detection Access Method and Physical Layer Specifications, Sep. 2006, IEEE Std. 802.3an.  D. J. C. MacKay and R. M. Neal, “Near Shannon limit performance of low density parity check codes,” Electron. Lett., vol. 32, no. 18, pp. 1645-1646, Aug. 1996.  N. Wiberg, “Codes and Decoding on General Graphs,” Ph.D. thesis, Linkoping University, Sweden, 1996.  D. J. C. MacKay, “Gallager codes that are better than turbo codes,” in Proc. 36th Allerton Conf. Communications, Control, and Computing, Sept. 1998.  E. M. Kurtas,A. V. Kuznetsov,I. Djurdjevic, “System perspectives for the application of structured LDPC codes to data storage devices,” IEEE Trans. On Magnetics, vol. 42, no. 2, Feb. 2006.  L. Chen, J. Xu, I. Djurdjevic, and S. Lin, “Near Shannon limit Quasi-Cyclic Low Density Parity Check Codes,” IEEE Trans. On Communications, vol. 52, no.7, July 2004.  J. Membe and J. M. F. Moura, “Partition-and-shift LDPC codes,” IEEE Transactions on Magnetics, vol. 41, no. 10, Oct. 2005.  X. Y. Shih, C. Z. Zhan, and A. Y. Wu, “A 7.39mm2 76mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications,” IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 301-304, Nov. 2008.  F. R. Kshischang and B. J. Frey, “Iterative decoding of compound codes by peobability propagation in graphical models,” IEEE Journal on Selected Areas in Communications, vol. 16, pp.219-230, Feb. 1998.  J. Hagenauer, E. Offer, L. Papke, “Iterative decoding of binary block and convolutional codes,” IEEE Trans. On Inform. Theory, vol. 42, no. 2, pp.429-445, March 1996.  J. Zang, M. Fossorier, “Shuffled iterative decoding,” IEEE Trans. Commun., vol. 53, no. 2, pp. 209-213, Feb. 2005.  D. Hocevar, “A reduced complexity decoder architecture via layered decoding of LDPC codes,” in Proc. IEEE Workshop on SiPS., pp. 107-112, Oct. 2004.  K. Zhang, X. Huang, Z. Wang, “High-Throughput layered decoder Implemen- tation for Quasi-Cyclic LDPC codes,” IEEE JSAC, vol. 27, no. 6, Aug.2009.  A. Blanksby and C. Howland, “A 690-mw 1-Gb/s 1024-b,rate-1/2 low-density parity-check code decoder,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404-412, Mar. 2002.  E. Yeo, B. Nikolic and V. Anantharam, “Architectures and implementations of Low density parity check decoding algorithms,” in Proc. Midwest Symposium on Circuits and Systems, vol. 3, pp. 437-440, Aug. 2002.  M. M. Mansour and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-State Circuits, vol. 41, pp. 684-698, Mar. 2006.  X. Y. Shih, C. Z. Zhan, and A. Y. Wu, “A 7.39mm2 76mW(1944,972) LDPC decoder chip for IEEE 802.11n applications,” IEEE Asian Solid-State Citcuits Conf. (ASSCC), pp. 301-304, Nov. 2008.  A. Darabiha, A. C. Carusone, and F. R. Kschischang, “Power reduction techn- iques for LDPC decoders,” IEEE J. Solid-State Circuits, vol. 43, no. 8, pp. 1835-1845, Aug. 2008.  H.-Y. Hsu, A.-Y. Wu, and J.-C. Ye, “Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems,” IEEE Trans. Circuits and System II, Exp. Briefs, vol. 53, no. 11, pp. 1245-1249, Nov 2006.  M. M. Mansour and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-State Circuits, vol. 41, pp. 684-698, Mar. 2006.  C.-H. Liu, S.-W. Yen, C.-L. Chen, H.-C. Chang, C.-Y. Lee, Y.-S. Hsu, and S.-J. Jou, “An LDPC decoder chip based on self-routing network for IEEE 802.16e applications,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 684-694, Mar. 2008.  Xin-Yu Shin, Cheng-Zhou Zhan, Chen-Hung Lin, and An-Yeu (Andy) Wu, An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System In 0.13um CMOS Process,” IEEE J. Solid-State Circuits, vol. 43, NO. 3, pp. 672 - 683, Mar. 2008.  Bo Xiang, Rui Shen, An Pan, Dan Bao, and Xiaoyang Zeng, “An Area-Efficient and Low-Power Multirate decoder for Quasi-Cyclic Low-Density Parity-Check Codes”, IEEE, Transactions on VLSI Systems,vol. 18, no. 10,Oct.2010.  Bo Xiang, Dan Bao, Shuangqu Huang, and Xiaoyang Zeng, “An 847-955 Mb/s 342-397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 um CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 1416-1432, June 2011.  Zhixiang CHEN, Xiao PENG, Xiongxin ZHAO, Qian XIE, Leona OKAMURA, Dajiang ZHOU and Satoshi GOTO, “A Macro-Layer Fully Parallel Layered LDPC Decoder SOC for IEEE 802.15.3c Application,” International Symposium on VLSI-DAT,pp 1-4, 2011.  Y. Miyata, K. Kubo, H. Yoshida, and T. Mizuochi, “Proposal for frame structure of optical channel transport unit employing LDPC codes for 100 Gb/s FEC,” Optical Fiber Communications, pp. 1-3, Mar. 2009.  M. M. Mansour and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-State Circuits, vol. 41, pp. 684-698, Mar. 2006.  K. K. Gunnam, G. S. Choi, and Mark B. Yeary, “A parallel VLSI architecture for layered decoding for array LDPC codes,” VLSI Design, pp. 738-743, Jan. 2007.  A. Darabiha, A. C. Carusone, and F. R. Kschischang, “Power reduction techniques for LDPC decoders,” IEEE J. Solid-State Circuits, vol. 43, no. 8, pp. 1835-1845, Aug. 2008.  K. Zhang, X. Huang, Z. Wang, “High-Throughput layered decoder implementation for Quasi-Cyclic LDPC codes,” IEEE JSAC, vol. 27, no. 6, Aug. 2009.  Z. Zhang, V. Anantharam, M. J. Wainwright, and B. Nikolic, “An efficient 10GBase-T Ethernet LDPC decoder design with low error floors,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 843-855, Apr. 2010.  T. Richardson, “Error floors of LDPC codes,” in Proc. Allerton Conf. Commun., Control, Computing, Monticello, IL, pp. 1426-1435, Oct. 2003.  Z. Zhang, L. Doleck, B.Nikolic, V. Anantharam, and M. Wainwright, “Lowering LDPC Error Floors by Postprocessing,” Proc. IEEE on Clob. Tlelcom, Conf. Cannes, France, Dec. 2008, pp.1-6.  Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. J. WainWright, “Design of LDPC Decoders for Improved Low Error Rate Performance: Quantization and Algorithm Choices,” IEEE Commun. Lett., vol. 7, pp. 317-319, Jul. 2003.  Jingyu Kang, Qin Huang, Shu Lin, and Khaled Abdel-Ghaffar, “An Iterative Decoding Algorithm with Backtracking to Lower the Error-Floors,” IEEE Transactions on Communications, vol. 59, pp. 64-73, 2011.||摘要:||
本論文提出應用於16-QAM之無線光載射頻通道(Radio over Fiber, ROF)之多碼率LDPC解碼器 VLSI設計與實作。本主題有幾個主要的重點 : (1).建構三個分割轉移LDPC Code (Partition and Shift LDPC, PS-LDPC)，其查核矩陣分別為(480，2400)、(800，2400)以及(480，4800)，碼率分別是4/5、2/3以及9/10，其Girth分別為8、6、6，三者都具有優秀的更正能力。(2).利用化簡後的Layered Min Sum Algorithm搭配LLR數值量化擴增的方式，在硬體複雜度不高的同時，亦能達到良好的效能。(3).LDPC解碼器架構採用雙路徑部分平行式架構，在切管線使頻率上升的同時，亦不造成電路閒置的情形，使傳輸率倍增。 (4).三個查核矩陣盡量共用硬體，包括計算單元與暫存器的硬體共用技巧，來減少所需耗費的面積。使用聯華電子UMC 90nm CMOS技術實作後，晶片核心面積為8.19 ，在電壓供應0.9伏特時，最高工作頻率為110MHz。固定解碼次數8次下，此三個查核矩陣(480，2400)、(800，2400)、(480，4800)所對應的傳輸率分別為5.5Gbps、3.3Gbps、2.75Gbps，其功率消耗分別為332.7mW、339.5mW、368.6mW。
其次，本論文針對LDPC解碼器常發生之錯誤基數(Error Floor)進行研究與探討。此議題可在LDPC解碼器之後加RS解碼器解決，我們利用UMC 90nm 實作4/5碼率之LDPC加RS解碼器晶片，在0.9V供應電壓下，經過實際量測後RS解碼器最高頻率為202M Hz，LDPC解碼器最高頻率為67.33MHz。傳輸率可以達到3.58Gbps，核心電路功耗為63.12mW。本論文亦提出了第二種有效降低Error Floor的演算法，此演算法共分2個階段，都是在LDPC完成解碼之iteration後才實施，當作「後處理」的動作。第一階段為Check Node Tracing Method，利用解碼完後判斷Unsatisfied 查核點的位置，往前追朔並找出重疊的變數點，把大部分錯誤更正回來；第二階段為Reduced-Back-Tracking Method，主要是用來解決少數剩餘的錯誤，而這些錯誤大部分是Absorbing Set的結構。我們從16 QAM通道解調端所接收的LLR值，利用4-bit量化的模擬，在解碼之後採用了本論文所提出的後處理方式，的確會比沒使用後處理的情況更能有效的降低Error Floor的發生，由於減少運算所需的位元數，預期可減小硬體複雜度，同時保有優良的解碼效能。
In this thesis, VLSI implementation of a multi-rate low-density parity-check (LDPC) decoder used in 16-QAM Radio over Fiber (ROF) channel is presented with four important features. The first is constructing three Partition and Shift LDPC (PS-LDPC) Codes with the parity check matrices (H) of (480, 2400), (800, 2400) and (480, 4800)corresponding to the coding rates of 4/5, 2/3, 9/10, and girths of 8, 6, 6, respectively. Secondly, good performance was achieved by a modified Layered Min Sum algorithm using quantization expansion of log likelihood ratio for less hardware complexity. The third is the proposed dual path partial parallel architecture using pipeline can increase the operating frequency, and double the throughput with the little circuit overhead. The last feature is the three LDPC codes share the hardware as much as possible, including the computing units and registers to reduce the chip area. Using the UMC 90nm COMS technology, the maximum frequency reaches 110MHz with the core area of 8.19mm2 at supply voltage of 0.9V. With 8 iterations per decoding process, the throughputs of PS-LDPC codes (480, 2400), (800, 2400) and (480, 4800) are 5.5Gbps, 3.3Gbps, 2.75 Gbps with the power consumptions of 332.7mW, 339.5mW and 368.6mW, respectively.
The error floor is the other common issue in LDPC decoders. This problem can be solved by adding the Reed-Solomon (RS) decoder after the LDPC decoder. It was fabricated using the UMC 90 nm CMOS process for the coding rate of 4/5. The measured maximum frequency of RS decoder is 202MHz, and the measured maximum frequency of LDPC decoder is 67.33MHz at supply voltage of 0.9V. The throughput is 3.58 Gbps and the power consumption is 63.12mW. The other method to lower the error floor employs the post-processing technique. It consists of two steps after the normal LDPC decoding procedures. The first step is called Check Node Tracing Method. By checking the locations of unsatisfied check nodes, the overlapped variable nodes may be traced, and their values are flipped to the correct values. The second step is called Reduced-Back-Tracking Method. The main objective is to correct the remaining errors. Most of them are induced by the absorbing sets. The simulation results show that the error floor is significantly improved for 4-bit Log likelihood ratios in 16-QAM demodulation. It is convinced that it can reduce hardware complexity due to less quantization bits, while keeping good decoding performance.
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