Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6241
標題: 16-QAM 無線光纖傳輸系統之多碼率低密度同位元查核碼解碼器實作與後處理器研究
Implementation and Study of Post Processors for Multi-Rate LDPC Decoders in 16-QAM Radio-Over-Fiber Systems
作者: 蕭家州
Hsiao, Chia-Chou
關鍵字: 多碼率;16-QAM;低密度同位元查核碼解碼器;無線光纖傳輸;錯誤基數;里德索羅門碼;後處理;Low Density Parity Check;multi-rate;Radio Over Fiber;Layered Min Sum Algorithm;error floor;Reed-Solomon;Check Node Tracing Method;Reduced-Back-Tracking Method;Absorbing set;trapping set;post-processing
出版社: 電機工程學系所
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摘要: 
本論文提出應用於16-QAM之無線光載射頻通道(Radio over Fiber, ROF)之多碼率LDPC解碼器 VLSI設計與實作。本主題有幾個主要的重點 : (1).建構三個分割轉移LDPC Code (Partition and Shift LDPC, PS-LDPC),其查核矩陣分別為(480,2400)、(800,2400)以及(480,4800),碼率分別是4/5、2/3以及9/10,其Girth分別為8、6、6,三者都具有優秀的更正能力。(2).利用化簡後的Layered Min Sum Algorithm搭配LLR數值量化擴增的方式,在硬體複雜度不高的同時,亦能達到良好的效能。(3).LDPC解碼器架構採用雙路徑部分平行式架構,在切管線使頻率上升的同時,亦不造成電路閒置的情形,使傳輸率倍增。 (4).三個查核矩陣盡量共用硬體,包括計算單元與暫存器的硬體共用技巧,來減少所需耗費的面積。使用聯華電子UMC 90nm CMOS技術實作後,晶片核心面積為8.19 ,在電壓供應0.9伏特時,最高工作頻率為110MHz。固定解碼次數8次下,此三個查核矩陣(480,2400)、(800,2400)、(480,4800)所對應的傳輸率分別為5.5Gbps、3.3Gbps、2.75Gbps,其功率消耗分別為332.7mW、339.5mW、368.6mW。

其次,本論文針對LDPC解碼器常發生之錯誤基數(Error Floor)進行研究與探討。此議題可在LDPC解碼器之後加RS解碼器解決,我們利用UMC 90nm 實作4/5碼率之LDPC加RS解碼器晶片,在0.9V供應電壓下,經過實際量測後RS解碼器最高頻率為202M Hz,LDPC解碼器最高頻率為67.33MHz。傳輸率可以達到3.58Gbps,核心電路功耗為63.12mW。本論文亦提出了第二種有效降低Error Floor的演算法,此演算法共分2個階段,都是在LDPC完成解碼之iteration後才實施,當作「後處理」的動作。第一階段為Check Node Tracing Method,利用解碼完後判斷Unsatisfied 查核點的位置,往前追朔並找出重疊的變數點,把大部分錯誤更正回來;第二階段為Reduced-Back-Tracking Method,主要是用來解決少數剩餘的錯誤,而這些錯誤大部分是Absorbing Set的結構。我們從16 QAM通道解調端所接收的LLR值,利用4-bit量化的模擬,在解碼之後採用了本論文所提出的後處理方式,的確會比沒使用後處理的情況更能有效的降低Error Floor的發生,由於減少運算所需的位元數,預期可減小硬體複雜度,同時保有優良的解碼效能。

In this thesis, VLSI implementation of a multi-rate low-density parity-check (LDPC) decoder used in 16-QAM Radio over Fiber (ROF) channel is presented with four important features. The first is constructing three Partition and Shift LDPC (PS-LDPC) Codes with the parity check matrices (H) of (480, 2400), (800, 2400) and (480, 4800)corresponding to the coding rates of 4/5, 2/3, 9/10, and girths of 8, 6, 6, respectively. Secondly, good performance was achieved by a modified Layered Min Sum algorithm using quantization expansion of log likelihood ratio for less hardware complexity. The third is the proposed dual path partial parallel architecture using pipeline can increase the operating frequency, and double the throughput with the little circuit overhead. The last feature is the three LDPC codes share the hardware as much as possible, including the computing units and registers to reduce the chip area. Using the UMC 90nm COMS technology, the maximum frequency reaches 110MHz with the core area of 8.19mm2 at supply voltage of 0.9V. With 8 iterations per decoding process, the throughputs of PS-LDPC codes (480, 2400), (800, 2400) and (480, 4800) are 5.5Gbps, 3.3Gbps, 2.75 Gbps with the power consumptions of 332.7mW, 339.5mW and 368.6mW, respectively.

The error floor is the other common issue in LDPC decoders. This problem can be solved by adding the Reed-Solomon (RS) decoder after the LDPC decoder. It was fabricated using the UMC 90 nm CMOS process for the coding rate of 4/5. The measured maximum frequency of RS decoder is 202MHz, and the measured maximum frequency of LDPC decoder is 67.33MHz at supply voltage of 0.9V. The throughput is 3.58 Gbps and the power consumption is 63.12mW. The other method to lower the error floor employs the post-processing technique. It consists of two steps after the normal LDPC decoding procedures. The first step is called Check Node Tracing Method. By checking the locations of unsatisfied check nodes, the overlapped variable nodes may be traced, and their values are flipped to the correct values. The second step is called Reduced-Back-Tracking Method. The main objective is to correct the remaining errors. Most of them are induced by the absorbing sets. The simulation results show that the error floor is significantly improved for 4-bit Log likelihood ratios in 16-QAM demodulation. It is convinced that it can reduce hardware complexity due to less quantization bits, while keeping good decoding performance.
URI: http://hdl.handle.net/11455/6241
其他識別: U0005-0708201120402700
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