Please use this identifier to cite or link to this item:
標題: 深次微米元件之淺接面製作
Ultrashallow Junction Formation for Deep Sub-micron Device
作者: 詹宜陵
Jang, Yi Ling
關鍵字: ultra-shallow-junction;淺接面;deep-submicron
出版社: 電機工程學系
為了未來在超大型積體電路上的應用 0.1微米通道長度的電晶體已被持續的研究。當元件尺寸小於0.18微米 甚至更小時 為了防止短通道效應 超淺的源極及汲極接面深度是必須的。
在本論文中 我們提出一種方法可以同時形成p+/n及n+/p 極淺接
面。利用很薄氮化矽層 在低能量離子佈植及快速熱處理後 可得超淺接面。p+/n接面深度為25至35 nm  片電阻值為1500至3050 Ω/ ; n+/p 接面深度為45 至55 nm  電阻值為772至1012 Ω/;而P型及N型金氧半元件(閘極長度為0.15微米;閘極氧化層厚度為2.5 nm)之臨界電壓變化在0.1伏特以內。驅動電流分別是175/373 uA/um 截止電流分別是4.1/0.69 pA/um。另外熱載子信賴度測試中由於閘極氧化層變薄使得介面狀態電荷密度上升的效應遠大於閘極電子捕捉效應,使得元件退化行為異於傳統較厚閘極的退化行為。

CMOS technology is being scaled down to 0.1 um gate length and to power supply of 1.2 V for applications of high density. Many challenges are observed at this technology node including formation of shallow junction, choice of gate dielectric. In this thesis, we investigated the impact of shallow source/drain extension on the characteristics of short channel PMOSFETs and NMOSFETs with gate length down to 0.15 um. We fabricated ultra-shallow junctions by implantation through the screen nitride layer. Ultrashallow p+/n junctions can be obtained with depth of 25-35 nm and sheet resistance of 3050 to 1500 Ω/□, while 45-55 nm and sheet resistance of 1012 to 772 Ω/□ for n+/p. These devices show output I-V characteristics for 1.8V NMOS and PMOS, with Ion =373 uA/um and 175 uA/um (VD=VG=1.8V) respectively. With the ITN method, the variation of threshold voltage is less than 100 mV in the channel length of 0.15 um. With the thickness of gate oxide is reduced, the increasing of the interface state is the major factor of the degradation induced by hot carrier stress.
Appears in Collections:電機工程學系所

Show full item record

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.