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標題: 1.5伏特 900MHz CMOS 鎖相迴路
1.5V 900MHz CMOS Phase-Locked Loop
作者: 郭隆質
Kuo, Lung-Chih
關鍵字: Phase-Locked Loop;鎖相迴路;Frequency Synthesis;Frequency Generator;頻率合成器;頻率產生器
出版社: 電機工程學系
本篇論文描述一個可以工作在1.5伏特900MHz之CMOS鎖相迴路系統,它包括:(1)相位/頻率偵測器(Phase/Frequency Detector),(2)電荷充放式電路(Charge-Pump Circuit),(3)低通濾波器(Low-Pass Filter),(4)壓控振盪器(Voltage-Controlled Oscillator,(5)多係數除頻器(Multi-Scale Divider)。此鎖相迴路,可以被運用在低電壓無線通訊系統中,提供內部的振盪頻率。
所提出的鎖相迴路系統中,所有的電路皆採用差動對電路,以產生完全差動的信號,並減少輸入雜訊的影響。相位/頻率偵測器用來偵測外部參考信號與內部除頻後的信號間的相位及頻率差,產生UP和DN的充放電的數位控制信號。電荷充放式電路接收相位/頻率偵測器的輸出信號,把偵測出來的相位差轉換成相對的電壓差,用來調變電壓控制振盪器的振盪頻率。低通濾波器由二階RC電路組成,用途在濾掉電荷充放式電路所輸出的高頻訊號成份。電壓控制振盪器,採用環形振盪器架構(Ring-Oscillator),由CMOS拴鎖式差動對組成內部延遲單元(Delay-Cell),接受控制信號調變延遲單元的延遲時間,以調變輸出的頻率。多係數除頻器,採用非同步計數架構,可提供除8及12,兩個除數; 其最高可除頻率為1.2GHz。此鎖相迴路系統中,除了電荷充放式電路,需額外的偏壓電路外,其它關鍵電路,皆不需偏壓電路,所以容易操作在低供應電壓下,且大大減少整體的晶片面積。
此鎖相迴路系統是使用TSMC 0.35μm CMOS 1P4M 的製程技術來模擬與製作。包含pads的晶片面積為1.08 mm ×1.01mm,消耗功率是9.17mW。

This thesis describes a 1.5 V 900 MHz CMOS phase-locked loop (PLL), which is composed of a phase/frequency detector (PFD), a charge-pump (CP), a low-pass filter (LF), a voltage-controlled oscillator (VCO) and a multi-scale frequency divider (FD). This PLL can be employed in the low-power wireless communication system to provide the internal oscillation frequency.
In the proposed PLL system, the differential-pair structure is used to produce the fully-differential signals and to reduce the influence of the injected noise. The PFD detects the phase and frequency error of the reference frequency and the divider output, and produces the UP and DN signals. The CP transfers the digital signals, UP and DN, to a relative voltage difference to change the frequency of the VCO. The function of the second-order LF composed of R and C is to filter the high frequency component of the output signal of the CP. The VCO employs the ring-oscillator structure. In it, the delay cell consists of a CMOS latch differential-pair and changes the delay time by the control voltage. The FD employs the asynchronous counter structure to provide two scales, 8 and 12. The highest input frequency of the FD is 1.2 GHz. In the PLL system, except CP, the other key components don't need the bias circuit. Thus, the system is suitable for low-power operation and largely reduces the area of the chip.
The proposed PLL is simulated and implemented by the TSMC 0.35μm CMOS 1P4M technology. The total chip area is 1.08 mm × 1.01 mm, including pads. The power consumption is 9.17mW.
Appears in Collections:電機工程學系所

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