Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6271
標題: 多值邏輯雙浮動閘快閃式記憶體之設計與分析
The Design and Analysis of Multi-Level Dual Floating Gate Flash Memories
作者: 陳泰元
Chen, Tai-Yuan
關鍵字: flash;快閃式記憶體;multi-level;Dual floating gate;多值邏輯;雙浮動閘
出版社: 電機工程學系
摘要: 
中文摘要
廣泛的應用於可攜式資訊產品標準週邊與通訊產品的快閃式記憶體,對於高記憶體密度的要求,多值邏輯準位快閃式記憶體技術,是可以實現同時又具備經濟效益的方法。以往的多值邏輯準位快閃式記憶體技術,大多利用不同的閘極偏壓或不同的源極/汲極脈衝長度,以控制不同的電荷量來儲存於浮動閘中,達成多值邏輯準位的實現,然而,這卻使得週邊電路變得更加複雜。在本論文中,我們提出了一改良型的雙浮動閘快閃式記憶體元件與其合適的操作方式。由於該元件具有不同的源極/汲極摻雜濃度與摻雜能量,使得產生4個邏輯準位不再需要變換不同的閘極電壓,同時,元件以通道熱電子(CHE)和汲極壘增熱電子(DAHE)來進行寫入,而浮動閘所儲存的電子則以通道福樂-諾漢(FN)穿隧機制來抹除,抹除後隨即利用基底熱電子再寫入法來改善臨界電壓分散的情況。藉由寫入時的干擾分析,我們依據分析結果來找出較合適的記憶體陣列,此外,在未被選擇到的字元線上施加一小電壓,達到抑制嚴重干擾情況的效果。由以上分析結果可以看出,此改良型的雙浮動閘快閃式記憶體元件,可以很容易的在單一元件上儲存更多位元的資料,同時需改變閘極電壓的次數也遠少於傳統技術,所以說,改良型的雙浮動閘快閃式記憶體元件將是多值邏輯快閃式記憶體中,能很容易就儲存更多位元資料的良好選擇。

Abstract
The feasibility of multilevel Flash E2PROM cells has been discussed to increase density of bits per unit area. In the prior arts, to control the charge stored in the floating gate for multilevel operation, variable voltages or pulses are applied to the control gate or the drain/source junctions. The peripheral circuits become more complicated. In this thesis, modification of dual floating gate (DFG) Flash cell and operation scheme is proposed. Due to the different source and drain doping concentrations and doping energies, it is not required to generate different voltages to achieve 4-level operation. The cell is programmed by Drain avalanche hot electrons (DAHE) and Channel hot electrons (CHE), while erased by channel Fowler-Nordheim (FN) tunneling to remove the charge in the floating gates (FG's). After erase, the threshold voltage spread can be tightened by the Substrate hot electrons (SHE) re-programming technique. By analysis of program disturbance, a more suitable cell array for DFG Flash memories is also proposed. In order to inhibit the serious disturbance, a low voltage is applied to the unselected word lines. Based on the above analysis, the DFG Flash cell can store more bits per cell with less efforts in peripheral circuits, easily can be designed, since less voltage variation is required. Therefore, it should be a good candidate for multilevel Flash memories in the future.
URI: http://hdl.handle.net/11455/6271
Appears in Collections:電機工程學系所

Show full item record
 

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.