Please use this identifier to cite or link to this item:
標題: 多值邏輯雙浮動閘快閃式記憶體之設計與分析
The Design and Analysis of Multi-Level Dual Floating Gate Flash Memories
作者: 陳泰元
Chen, Tai-Yuan
關鍵字: flash;快閃式記憶體;multi-level;Dual floating gate;多值邏輯;雙浮動閘
出版社: 電機工程學系

The feasibility of multilevel Flash E2PROM cells has been discussed to increase density of bits per unit area. In the prior arts, to control the charge stored in the floating gate for multilevel operation, variable voltages or pulses are applied to the control gate or the drain/source junctions. The peripheral circuits become more complicated. In this thesis, modification of dual floating gate (DFG) Flash cell and operation scheme is proposed. Due to the different source and drain doping concentrations and doping energies, it is not required to generate different voltages to achieve 4-level operation. The cell is programmed by Drain avalanche hot electrons (DAHE) and Channel hot electrons (CHE), while erased by channel Fowler-Nordheim (FN) tunneling to remove the charge in the floating gates (FG's). After erase, the threshold voltage spread can be tightened by the Substrate hot electrons (SHE) re-programming technique. By analysis of program disturbance, a more suitable cell array for DFG Flash memories is also proposed. In order to inhibit the serious disturbance, a low voltage is applied to the unselected word lines. Based on the above analysis, the DFG Flash cell can store more bits per cell with less efforts in peripheral circuits, easily can be designed, since less voltage variation is required. Therefore, it should be a good candidate for multilevel Flash memories in the future.
Appears in Collections:電機工程學系所

Show full item record

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.