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標題: 十億赫茲取樣頻率開迴路殘值增益六位元管線式類比數位轉換器
A 6-bit 1GHz Sample Rate Pipelined Analog-to-Digital Converter With Open-Loop Residue Amplifiers
作者: 蘇純緯
Su, Chung-Wei
關鍵字: pipelined;管線式;open-loop;residue amplifier;gain control;開迴路;殘值放大器;增益控制
出版社: 電機工程學系所
引用: [1] D.-L. Shen and T.-C. Lee, “A 6-b 800-MS/s Pipelined A/D Converter with Open-Loop Amplifiers”, IEEE Journal of Solid-State Circuit, Vol. 42, No. 2, pp. 258-268, February 2006. [2] F.-C. Hsieh, “A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification”, National Taiwan University, Master Thesis, July 2008. [3] L. Picolli, P. Malcovati, L. Crespi, F. Chaahoub and A. Baschirotto, “A 90nm 8b 120Ms/s-250Ms/s Pipeline ADC”, ESSCIRC 34th European Solid-State Circuits Conference, pp. 266-269, September 2008. [4] Y.-J. Cho, K.-H. Lee, H.-C. Choi, Y.-J. Kim, K.-J. Moon and S.-H. Lee, “A dual-channel 6b 1GS/s 0.18um CMOS ADC for ultra wide-band communication systems”, IEEE Asia Pacific Conference Circuits & Systems, pp. 339-342, December 2006. [5] P.M. Figueiredo, P. Cardoso, A. Lopes, C. Fachada, N. Hamanishi, K. Tanabe and J. Vital, “A 90nm CMOS 1.2V 6b 1GS/s two-step subranging ADC”, IEEE International Solid-State Circuits Conference, pp. 2320-2329, February 2006. [6] C.-H. Chang, “A Low-Power 8-bit 200-MS/s Fully Differential CMOS Pipeline A/D Converter”, National Chung-Hsing University, Master Thesis, July 2005. [7] B.-Y. Cheng, “Doubled Sampling 100MS/s 10 Bit Fully Differential Pipelined Analog-to-Digital Converter”, National Chung-Hsing University, Master Thesis, January 2007. [8] B. Murmann and B. E. Boser, “A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”, IEEE Journal of Solid-State Circuit, Vol. 38, No. 12, pp. 2040-2050, December 2003. [9] K.-W. Cheng, “A 1.0-V, 10-bit COMS Pipelined Analog-to-Digital Converter,” National Taiwan University, Master Thesis, June 2002. [10] C.-M. Liu, “8-bit, High Conversion Rate Pipelined ADC with Improved Capacitor,” National Taiwan University, Master Thesis, June 2002. [11] C.-P. Wu, “A Programmable Gain Amplifier with Integrated RSSI Function for Wireless Communication Systems”, National Taiwan University, Doctor Thesis, July 2006. [12] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. [13] J. Shen and P. R. Kinget, “A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS”, IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp. 787-795, April 2008. [14] J. Li and U.-K. Moon, “A 1.8-V 67-mW 10-bit 100-MS/s Pipelined ADC Using Time-Shifted CDS Technique”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 9, pp. 1468-1476, September 2004. [15] H.-Y. Lee and S.-l. Liu, “A 8-bit 140MS/s Pipelined ADC Using Folded Sample-and-Hold Stage”, International Conference on Electron Devices and Solid-State Circuits, pp. 357-360, December 2007. [16] S.-M. Yoo, J.-B. Park, S.-H. Lee, and U.-K. Moon, “A 2.5-V 10-b 120-MSample/s CMOS Pipelined ADC Based on Merged-Capacitor Switching”, IEEE Transactions On Circuits And Systems—II: Express Briefs, Vol. 51, No. 5, pp. 269-275, May 2004. [17] Y.-J. Kim, H.-C. Choi, K.-H. Lee, G.-C. Ahn, S.-H. Lee, J.-H. Kim, K.-J. Moon, M. Choi, K.-H. Moon, H.-J. Park, and B.-H. Park, “A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC Based on Multi-Stage Amplifiers”, IEEE Custom Integrated Circuits Conference, pp. 271-274, September 2009. [18] S.-T. Ryu, S. Ray, B.-S. Song, G.-H. Cho and K. Bacrania, “A 14b-Linear Capacitor Self-Trimming Pipelined ADC”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 11, pp. 2046-2051, November 2004. [19] S. Ray and B.-S. Song, “A 13-b Linear, 40-MS/s Pipelined ADC With Self-Configured Capacitor Matching”, IEEE Journal of Solid-State Circuits, Vol. 42, No. 3, pp. 463-474, March 2007. [20] N. Sasidhar, Y.-J. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. K. Hanumolu and U.-K. Moon, “A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, pp. 2392-2401, September 2009. [21] C.-C. Fan, “Low Power High Speed 8-bit Pipelined A/D Converter for RGB Image Processing”, National Chung Cheng University, Master Thesis, July 2005. [22] J.-M. He, “Low Power Techniques for Pipelined ADCs”, National Chung Cheng University, Master Thesis, August 2008. [23] H. Dinç and P. E. Allen, “A 1.2 GSample/s Double-Switching COMS THA With -62 dB THD”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 3, pp. 848-861, March 2009. [24] T. Baumheinrich, B. Prégardier, and U. Langmann “A 1-GSample/s 10-b Full Nyquist Silicon Bipolar Track&Hold IC”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, pp. 1951-1960, December 1997 [25] B. Razavi, Principles of Data Conversion System Design, Wiley-IEEE Press, 1995. [26] K. Sushihara, H. Kimura, Y. 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在這篇論文中,我們描述了1個6位元1GS/s開迴路殘值放大器的管線式類比數位轉換器的實現與量測結果。在1.5位元轉換級的架構設計上,採用電壓模式的開迴路放大器,控制全域的增益放大級增益技術,使得所設計的管線式類比數位轉換器大幅地降低了在速度以及功率上取捨的嚴苛要求。測量結果顯示,在低頻率輸入下,其ENOB達到3.9-bit,優於高頻率輸入的解析度。量測到的DNL是在1.17 LSB和-1.19 LSB之間,和測量到的INL是在1.73 LSB和-1.57 LSB之間。總功率消耗為25mW。該晶片由TSMC 90nm CMOS Mixed Signal RF 1P9M CMOS技術製作,全部面積0.65mm X 0.65mm,核心面積為0.199mm X 0.144mm。

By aggressive device scaling in modern integrated circuit technology, the computing power of digital circuits increases significantly. But the low power supply and relative high threshold voltage of transistors exhibit design constraints for analog circuit. Analog-to-digital converters(ADCs) are the key components to connect the real world with the discrete-computation fields. Due to their extensive use of analog and mixed analog-digital operations, ADC often appears as the bottleneck in data processing applications, resulting in limiting the overall speed or precision.
In this thesis, we describe the implementation and measurement results of a 6-bit 1-GS/s pipelined ADC with open-loop residue amplification. Employing voltage-mode open-loop amplifiers in 1.5-bit conversion per stage, global gain control techniques in gain stages, the proposed ADC relaxes stringent design tradeoffs between speed and power. The measurement results achieves ENOB of 3.9-bit for low frequency input that is better than high frequency input for resolution. The measured DNL is within 1.17 LSB and -1.19 LSB and the measured INL is within 1.73 LSB and -1.57 LSB. The total power dissipation is 25 mW. The chip is fabricated in a TSMC 90nm CMOS Mixed Signal RF 1P9M CMOS technology, the all area is 0.65mm X 0.65mm and the core area is 0.199mm X 0.144mm.
其他識別: U0005-0905201116265400
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