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dc.contributorShuenn-Yuh Leeen_US
dc.contributorHao-Chiao Hongen_US
dc.contributor.advisorChing-Yuan Yangen_US
dc.contributor.authorSu, Chung-Weien_US
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Moon, “A 2.5-V 10-b 120-MSample/s CMOS Pipelined ADC Based on Merged-Capacitor Switching”, IEEE Transactions On Circuits And Systems—II: Express Briefs, Vol. 51, No. 5, pp. 269-275, May 2004. [17] Y.-J. Kim, H.-C. Choi, K.-H. Lee, G.-C. Ahn, S.-H. Lee, J.-H. Kim, K.-J. Moon, M. Choi, K.-H. Moon, H.-J. Park, and B.-H. Park, “A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC Based on Multi-Stage Amplifiers”, IEEE Custom Integrated Circuits Conference, pp. 271-274, September 2009. [18] S.-T. Ryu, S. Ray, B.-S. Song, G.-H. Cho and K. Bacrania, “A 14b-Linear Capacitor Self-Trimming Pipelined ADC”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 11, pp. 2046-2051, November 2004. [19] S. Ray and B.-S. Song, “A 13-b Linear, 40-MS/s Pipelined ADC With Self-Configured Capacitor Matching”, IEEE Journal of Solid-State Circuits, Vol. 42, No. 3, pp. 463-474, March 2007. [20] N. Sasidhar, Y.-J. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. K. Hanumolu and U.-K. Moon, “A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, pp. 2392-2401, September 2009. [21] C.-C. Fan, “Low Power High Speed 8-bit Pipelined A/D Converter for RGB Image Processing”, National Chung Cheng University, Master Thesis, July 2005. [22] J.-M. He, “Low Power Techniques for Pipelined ADCs”, National Chung Cheng University, Master Thesis, August 2008. [23] H. Dinç and P. E. Allen, “A 1.2 GSample/s Double-Switching COMS THA With -62 dB THD”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 3, pp. 848-861, March 2009. [24] T. Baumheinrich, B. Prégardier, and U. Langmann “A 1-GSample/s 10-b Full Nyquist Silicon Bipolar Track&Hold IC”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, pp. 1951-1960, December 1997 [25] B. Razavi, Principles of Data Conversion System Design, Wiley-IEEE Press, 1995. [26] K. Sushihara, H. Kimura, Y. Okamoto, K. Nishimura and A. Matsuzawa, “A 6b 800MSamples/s CMOS A/D Converter”, IEEE International Solid-State Circuits Conference Session 26, pp. 428-429, 2000. [27] K. Sushihara and A. Matsuzawa, “A 7b 450MSample/s 50mW CMOS ADC in 0.3mm2”, IEEE International Solid-State Circuits Conference Session 10, pp. 170-172, February 2002. [28] K. Uyttenhove, A. Marques and M. Steyaert, “A 6-bit 1 GHz Acquisition Speed CMOS Flash ADC with Digital Error Correction”, IEEE Custom Integrated Circuits Conference, pp. 249-252, May 2000. [29] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley&Sons, 1996. [30] K. Martin, Digital Integrated Circuit Design, Oxford, New York, 2001.zh_TW
dc.description.abstract隨著積體電路製程持續進步,供給電壓與電晶體面積急速減小,數位的運算能力也不斷增加。但對類比電路而言,較低的供給電壓與相對較大的臨界電壓,反而造成了電路設計上的困難。類比數位轉換器是連結真實世界與離散運算領域的關鍵元件。由於在它的使用上延伸了純類比訊號與類比數位混和訊號的運作,類比數位轉換器往往成為了資料運算應用上的瓶頸,限制了整個系統的速度與精確度。 在這篇論文中,我們描述了1個6位元1GS/s開迴路殘值放大器的管線式類比數位轉換器的實現與量測結果。在1.5位元轉換級的架構設計上,採用電壓模式的開迴路放大器,控制全域的增益放大級增益技術,使得所設計的管線式類比數位轉換器大幅地降低了在速度以及功率上取捨的嚴苛要求。測量結果顯示,在低頻率輸入下,其ENOB達到3.9-bit,優於高頻率輸入的解析度。量測到的DNL是在1.17 LSB和-1.19 LSB之間,和測量到的INL是在1.73 LSB和-1.57 LSB之間。總功率消耗為25mW。該晶片由TSMC 90nm CMOS Mixed Signal RF 1P9M CMOS技術製作,全部面積0.65mm X 0.65mm,核心面積為0.199mm X 0.144mm。zh_TW
dc.description.abstractBy aggressive device scaling in modern integrated circuit technology, the computing power of digital circuits increases significantly. But the low power supply and relative high threshold voltage of transistors exhibit design constraints for analog circuit. Analog-to-digital converters(ADCs) are the key components to connect the real world with the discrete-computation fields. Due to their extensive use of analog and mixed analog-digital operations, ADC often appears as the bottleneck in data processing applications, resulting in limiting the overall speed or precision. In this thesis, we describe the implementation and measurement results of a 6-bit 1-GS/s pipelined ADC with open-loop residue amplification. Employing voltage-mode open-loop amplifiers in 1.5-bit conversion per stage, global gain control techniques in gain stages, the proposed ADC relaxes stringent design tradeoffs between speed and power. The measurement results achieves ENOB of 3.9-bit for low frequency input that is better than high frequency input for resolution. The measured DNL is within 1.17 LSB and -1.19 LSB and the measured INL is within 1.73 LSB and -1.57 LSB. The total power dissipation is 25 mW. The chip is fabricated in a TSMC 90nm CMOS Mixed Signal RF 1P9M CMOS technology, the all area is 0.65mm X 0.65mm and the core area is 0.199mm X 0.144mm.en_US
dc.description.tableofcontents摘要 i Abstract ii 目錄 iii 圖目錄 vi 表目錄 x 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機 2 1.3 論文架構 4 第二章 類比數位轉換器介紹 5 2.1 基礎類比數位轉換器參數與效能 5 2.1.1 輸入範圍 5 2.1.2 最小有效位元值 5 2.1.3 訊號雜訊比 5 2.1.4 訊號雜訊失真比 6 2.1.5 快速傅立葉轉換取樣 6 2.1.6 有效位元數 6 2.1.7 微分非線性度與積分非線性度 6 2.2 常見類比數位轉換器架構 10 2.2.1 快閃式類比數位轉換器 10 2.2.2 逐漸趨近式類比數位轉換器 12 2.2.3 二階式類比數位轉換器 14 2.2.4 管線式類比數位轉換器 16 2.2.5 分時並行式類比數位轉換器 18 2.3 近年來文獻探討 20 2.3.1 雙通道內插快閃式類比數位轉換器[4] 20 2.3.2 兩階式次範圍類比數位轉換器[5] 21 2.3.3 120MHz-250MHz取樣頻率管線式類比數位轉換器[3] 22 2.3.4 開迴路管線式類比數位轉換器[1] 23 2.3.5 本篇類比數位轉換器概要 24 第三章 管線式類比數位轉換器原理與架構 25 3.1 1.5位元轉換級 26 3.2 2.5位元轉換級 30 3.3 管線式類比數位轉換器的閉迴路架構 33 3.3.1 運算放大器設計規格與應用電路分析 34 3.3.2 切換開關電路分析 36 3.3.3 取樣電容 37 3.3.4 傳統的1.5位元管線式級使用閉迴路放大器 39 第四章 開迴路管線式類比數位轉換器 41 4.1 放大器的特性原理與電路架構 42 4.2 具有消除偏移誤差的追蹤保持放大器 47 4.3 MDAC級中的開迴路架構 50 4.4 殘值放大器電路架構 52 4.5 比較器電路 55 4.6 1.5位元子類比數位轉換器 57 4.7 2位元快閃式類比數位轉換器 59 4.8 仿製電路增益控制 61 4.9 同步電路與數位修正電路 63 4.10 開迴路管線式ADC模擬結果 68 4.11 整體電路架構佈局 72 第五章 實驗量測結果 74 5.1 量測方法 74 5.1.1 供應電壓調整電路 77 5.1.2 參考電壓電路 78 5.2 量測結果 79 5.3 近年來文獻比較 84 第六章 總結 86 參考文獻 88zh_TW
dc.subjectresidue amplifieren_US
dc.subjectgain controlen_US
dc.titleA 6-bit 1GHz Sample Rate Pipelined Analog-to-Digital Converter With Open-Loop Residue Amplifiersen_US
dc.typeThesis and Dissertationzh_TW
item.openairetypeThesis and Dissertation-
item.fulltextno fulltext-
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