Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6301
標題: 電流模式暨管線式類比/數位轉換器
Design of the Current-Mode Pipelined A/D Converter
作者: 黃俊騰
Huang, Chun-Teng
關鍵字: analog-to-digital converter;類比/數位轉換器;current-mode;low-voltage;電流模式;低電壓
出版社: 電機工程學系
摘要: 
近年來由於CMOS數位積體電路技術成功的應用在許多系統上,其系統的特性也高度取決於資料轉換器。本論文中設計一個操作在1.5伏特、10位元、取樣頻率為50MHz之電流模式、管線式類比/數位轉換器,以提供如高畫質電視等視訊、通訊、醫療影像系統之應用。設計中使用新的高速管線式架構,利用平行處理的方式來增加操作速度,並採用電流模式電路技術,以增加輸入訊號之動態範圍及降低功率消耗。此外,為了達到理想的高輸出速度、小面積及低消耗功率的特性,本論文採用每級兩位元的架構,各級轉換器是由高速和高解析度之零電壓開關取樣保持電路、時脈電壓倍增電路、高速電流比較器、電流減法器以及電流增益放大器所構成。本電路採用MOSIS 0.35μm雙多晶矽-參金屬層製程技術。由模擬結果顯示,電路之最大微分非線性誤差及積分非線性誤差分別為0.325LSB及0.7LSB,當取樣速率為50MHz時,整個電路功率消耗為30mW。

In recent days, the CMOS digital integrated circuits have been successfully utilized in many applications. It is highly relied on the data converters to improve the overall systems performance. This thesis describes the design of a 10-bit, 50-MS/s CMOS current-mode pipelined analog to digital converter (ADC), which is suitable for high-speed applications, such as HDTV, video, communication, and medical imaging systems. The proposed ADC is based on an enhanced architecture, which adopts the parallelism way to improve conversion rate. Furthermore, using current mode technique can increase the dynamic range of the input signal, achieve higher conversion speed and lower power. The architecture of each stage comprises a high-resolution high-speed current sample-and-hold, a bootstrap circuit, high-speed current comparators, a current subtractor, and a gain stage. The chip is designed by using the MOSIS 0.35m 2P3M CMOS technology. The simulation shows the peak differential and integral non-linearity (DNL and INL) of 0.325 LSB and 0.7 LSB when operated at a 50-MS/s-conversion rate and a power consumption of only 30 mW.
URI: http://hdl.handle.net/11455/6301
Appears in Collections:電機工程學系所

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