Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6304
標題: 可適應性直流對直流昇壓轉換器
An Adaptable DC-DC Boost Converter
作者: 江定達
Jiang, Ding-Da
關鍵字: dc-dc;直流對直流;dc to dc;boost converter;dc-dc converter;adaptable;switching regulator;switching converter;PFM;昇壓轉換器;直流轉換器;可適應性;切換式轉換器;脈衝頻率調變
出版社: 電機工程學系所
引用: [1] G. A. Rincon-Mora, P. E. Allen, “A low-voltage, low quiescent current, low drop-out regulator,” IEEE J. Solid-State Circuits, vol. 33, pp.36-44, Jan. 1998. [2] N. Mohan, T. M. Undeland and W. P. Robbins, Power Electronics: Converters, Applications, and Design, Second Ed., New York: Wiley & Sons, 1995. [3] Razavi B., Design of Analog CMOS Integrated Circuit, McGraw-Hill Companies, Inc. [4] Ka Nang Leung, P.K.T. Mok, “ A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device, ” IEEE J. Solid-State Circuit, vol. 37, pp. 526-529, April 2002. [5] G. A. Rincon-Mora and P. E. Allen, A 1.1-V Current-Mode and Piecewise-Linear Curvature-Corrected Bandgap Reference,”IEEE Journal of Solid-State Circuits, vol. 33, pp. 1551-1554, Oct. 1998. [6] Chi Yat Leung, Ka Nang Leung, P.K.T Mok, “Design of a 1.5-V high-order curvature-compensated CMOS bandgap reference,” IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 48-52, May. 2004. [7] Ming-Dou Ker; Jung-Sheng Chen; Ching-Yun Chu, “New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation,” IEEE International Symposium on Circuits and Systems, Vol. 4, pp. 3861-3864, May. 2005. [8] P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and Design of Analog Integrated Circuits, Wiley, New York, 2001. [9] E. Dallago, M. Passoni and G. Sassone, “Lossless Current Sensing in Low Voltage High Current DC/DC Modular Supplies”, IEEET Trans. Industrial Electronics, vol. 47, pp. 1249-1252, Dec. 2000. [10] P. Midya, M Greuel and P. Krein, “Sensorless Current Mode Control-An Observer Technique for DC- DC Converters”, IEEE Trans. Power Electronics, vol. 16, pp. 522 -526, July. 2001. [11] W. Schultz, “Lossless Current Sensing with SENSEFETs Enhances the Motor Drive”, Motorola technical report, 1988. [12] S.Yuvarajan, “Performance Analysis and Signal Processing in a Current Sensing MOSFET (SENSEFET)”, in Proc. Industry Applications Society Annual Meeting, vol. 2, pp. 1445 - 1450, 1990. [13] P. Givelin, M. Bafleur, “On-Chip Over Current and Open Load Detection for a Power MOS High Side Switch: A CMOS Current Source Approach”, in Proc. Fifth European Conference on Power Electronics and Applications, vol. 2, pp.197-200, 1993. [14] S. Yuvarajan and L. Wang, “Power Conversion and Control using a Current Sensing MOSFET”, in Proc. 34th Midwest Symposium on Circuits and Systems, vol. 1, pp.166-169,1992. [15] H.P. Forghani-zadeh and G.A. Rincon-Mora, “Current sensing techniques for DC-DC converters,”IEEE MWSCAS, pp. 577-580, 2002. [16] N. Li, F. Haviland, and A. Tuszynski, “A CMOS tapered buffer,” IEEE J. Solid-State Circuits, vol. 25, pp. 1005-1008, Aug. 1990. [17] C. Yoo, “A CMOS buffer without short-circuit power consumption,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 935-937, Sept. 2000. [18] “DC-DC Converter Tutorial,” Maxim Semiconductor Application Note, Maxim Inc.,2000 [19] W. Kester, B. Erisman, “Switch Regulators,” Analog Devices Technical Library on Power Management, 1999. [20] M. Gildersleeve,H. P. Forghani-zadeh, and G. A. Rincon-Mora, “Acomprehensive power analysis and a highly efficient, mode-hopping dc-dc converter,” Proc. ASIC'02, pp. 153-156, Aug. 6-8, 2002. [21] Mihajlovic, Z.; Lehman, B.; Chunxiao Sun, “Output ripple analysis of switching DC-DC converters,” IEEE Transactions on Circuits and Systems, vol. 5, pp.1596 - 1611 Aug. 2004. [22] Phillip E. Allen and Douglas, CMOS Analog Circuit Design, 2nd Edition, Oxford, 2002 [23] R. Gregorian, Introduction to CMOS Op-Amps and Comparators. New York: Wiley, 1999. [24] C. F. Lee and P. K. T. Mok, “A Monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 3-14, Jan. 2004. [25] H. Banda, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi,and K. Sakui, “A CMOS bandgap references with sub-1-V operation,” IEEE J. Solid-State Circuits, vol. 34, pp. 670-673, May
摘要: 
本論文針對目前既有的切換式轉換器調變技術,研究其優缺點,並以簡單,低成本為主軸來設計。目前切換式轉換器的控制方式有脈衝寬度調變(PWM)及脈衝頻率調變(PFM)兩種技術,其中PWM控制電路的穩定度較難設計,PFM電路較簡單且控制迴路穩定度高,效率方面,PWM輕載效率不佳,但PFM卻很好,重載則相反。以漣波來說PWM優於PFM。

統合以上特性,我們選擇電流模式(Current Mode)的脈衝頻率調變(PFM)來設計,並提出新的控制方法,稱為”Adaptable PFM Technology” 整合了PWM及PFM的優點,它的概念很簡單,當轉換器轉換能量給負載,而負載並不需要如此多的能量,剩下的能量就存放入電容,而產生了漣波,若我們可以針對不同負載需求來動態的變換充電能量,使負載吃多少才給多少能量,如此一來對於系統的輸出漣波可以大大的降低,而且不像PWM一樣在輕載下依然以高切換頻率工作,增加切換損耗,浪費能量。

在本篇論文中,我們使用台積電CMOS 0.35µm 2P4M 5V模型製程製作實現,晶片面積大約1.5 x 1.5 mm²,使用創新技術Adaptable PFM架構,該技術可依據外部負載大小自動調節頻率與工作週期來得到最佳的能量轉換。可適應性轉換器的平均效率大於70%,最大效率82%,與傳統PFM轉換器做模擬比較,在相同條件下,該轉換器的效率對負載效率曲線不但略高於傳統PFM轉換器,而且當負載電流為100毫安時輸出漣波降低了64.3%,解決傳統PFM為人垢病的問題,並且彌補了PWM在輕載下效率不佳的窘境。

In this thesis, existing modulation technology of switch regulator is investigated to design simple and low cost dc-dc converter. There are two control methods of existing switch regulators, i.e., pulse width modulation (PWM) and pulse frequency modulation (PFM), PWM control method is difficult to design in stability, while PFM is simple and high stability. In terms of efficiency, PWM has low efficiency in light load but high efficiency in heavy load. On the contrary, PFM has low efficiency in heavy load but low efficiency in light load. In terms of ripple PWM is better them PFM.

Regarding the above characteristics, we select PFM current mode control method to design, and propose a novel control method which is the adaptable PFM technology. Its concept is very simple. When the converter converts power to load, it the load does not need so much energy, the unnecessary energy transfers to ripple. Thus a converter is designed to adapt charge power to varying loading to get optimum power conversion. The converter output ripple could be greatly reduced and the power is saved.

This converter chip is designed and fabricated with TSMC 0.35µm 2P4M 5V Mixed Signal CMOS technology. The chip area is about 1.5 x 1.5 mm² and makes use of the novel technology of adaptable PFM. This technology can adapt frequency and duty cycle to varying loading to get optimum power conversion. The adaptable converter has average efficiency over 70% and maxima efficiency 82%. Under the same conditions, the efficiency of the adaptable converter higher than that of the conventional converter, However, the ripple is reduced about 64.3% than the conventional converters at 100mA loading current. This technology improves ripple in the PFM and efficiency in the PWM at light load.
URI: http://hdl.handle.net/11455/6304
其他識別: U0005-1207200621320900
Appears in Collections:電機工程學系所

Show full item record
 

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.