Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6318
標題: 可自我校正電容陣列之單端輸入十位元連續逼近式類比數位轉換器
A Self-calibrating 10-bit Single End Successive Approximation Register ADC
作者: 梁興彥
Liang, Shing-Yan
關鍵字: ADC;類比數位轉換器;DAC;Comparator;Calibration;Capacitor array;數位類比轉換器;比較器;校正;電容陣列
出版社: 電機工程學系所
引用: [1] Hao-Chiao Hong and Guo-Ming Lee,“A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC” IEEE J. Solid-State Circuits, vol. 42, no. 10, Oct. 2007. [2] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang and Ying-Zu Lin , “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure” IEEE J. Solid-State Circuits, vol. 45, no. 4, Apr. 2010. [3] He Yong, Wu Wuchen, Meng Hao and Zhou Zhonghua,“A 14-bit Successive-ApproximationAD Converter with Digital Calibration Algorithm” in 8th IEEE Int. Conf. ASIC, Sep. 2009 ,pp. 234-237. [4] Kuramochi Y.,Matsuzawa A. and Kawabata M., “A 0.05-mm2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS” IEEE Asian Solid-State Circuits Conf.(ASSCC.) Jul. 2007, pp. 224 - 227. [5] Wenbo Liu and Yun Chiu, “An Equalization-Based Adaptive Digital Background Calibration Technique for Successive Approximation Analog-to-Digital Converters,” in 7th IEEE Int. Conf. ASIC, 2007 ,pp. 289-292. [6] Behzad Razavi, “Principles of Data Conversion System Design,” New York: IEEE Press,1995. [7] Behzad Razavi, “Design of Analog COMS Intergrated Circuits,” McGraw-Hill Companies, Inc. 2001 [8] Hsin-Hung Ou and Bin-Da Liu, “A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques,” in Proc. ISCAS , May. 2005 ,pp. 1972-1975. [9] Kazuaki Deguchi, Naoko Suwa, Masao Ito, Toshio Kumamoto, and Takahiro Miki, “A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 10, Oct .2008 [10] A. Rossi and G. Fucili, “Nonredundant successive approximation register for A/D converters,” Electron. Lett., vol. 32, no. 12, Jun. 1996, pp. 1055–1057. [11] Andrew M. Abo and Paul R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp.599-606 May 1999. [12] Yanfei Chen, Xiaolei Zhu, Tamura H., Kibune M., Tomita Y., Hamada T., Yoshioka M., Ishikawa K., Takayama T., Ogawa J., Tsukamoto S. and Kuroda T., “Split capacitor DAC mismatch calibration in successive approximation ADC,” Custom Integrated Circuits Conf.(CICC), Sep. 2009, pp. 279-282. [13] Murmann B. “A/D Converter Trends: Power Dissipation, Scaling and Digitally Assisted Architectures, ” Custom Integrated Circuits Conf.(CICC), 2008, pp. 105-112. [14] Yoshioka M., Ishikawa K., Takayama T., Tsukamoto S., “A 10-b 50-MS/s 820uW SAR ADC With On-Chip Digital Calibration” IEEE J. Biomedical Circuits and System, vol. 4, no. 6, pp.410-416 Dec. 2010. [15] 陳柏予, “雙倍取樣100MS/s 10位元之全雙端雙管線式類比數位轉換器,”國立中興大學電機工程學系碩士班研究生畢業論文,中華民國九十七年一月。
摘要: 
本論文描述一10位元910KHz取樣率連續逼近式類比數位轉換器(SAR ADC),並加入校正機制進行校正,校正內部電容不匹配,使電路能達到之有效位元數(ENOB)提高。
在加入校正電路之前,輸入頻率為0.1倍取樣率之正弦波訊號,量測得到其ENOB為6.55bit,SNR值為41.19dB,INL為-16.69LSB~2.52LSB,DNL為-1LSB~9.919LSB,功率消耗4.58mW。
加入校正電路後,並改善取樣保持電路與類比數位電源區隔後,電路後模擬得到其結果:ENOB為8.78,SNR值為54.62dB,INL為-1.267LSB~3.66LSB,DNL為-1LSB~1.56LSB,功率消耗1.34mW。
在本論文校正機制中在某些情形會產生錯誤,將其錯誤改善後比較其電路前模擬之結果:改善前ENOB為9.74,SNR為61.44dB,改善其錯誤後ENOB為9.91,SNR為60.39dB。
URI: http://hdl.handle.net/11455/6318
其他識別: U0005-0908201116083600
Appears in Collections:電機工程學系所

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