Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6318
DC FieldValueLanguage
dc.contributor張順志zh_TW
dc.contributor揚清淵zh_TW
dc.contributor.advisor林維亮zh_TW
dc.contributor.author梁興彥zh_TW
dc.contributor.authorLiang, Shing-Yanen_US
dc.contributor.other中興大學zh_TW
dc.date2012zh_TW
dc.date.accessioned2014-06-06T06:37:52Z-
dc.date.available2014-06-06T06:37:52Z-
dc.identifierU0005-0908201116083600zh_TW
dc.identifier.citation[1] Hao-Chiao Hong and Guo-Ming Lee,“A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC” IEEE J. Solid-State Circuits, vol. 42, no. 10, Oct. 2007. [2] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang and Ying-Zu Lin , “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure” IEEE J. Solid-State Circuits, vol. 45, no. 4, Apr. 2010. [3] He Yong, Wu Wuchen, Meng Hao and Zhou Zhonghua,“A 14-bit Successive-ApproximationAD Converter with Digital Calibration Algorithm” in 8th IEEE Int. Conf. ASIC, Sep. 2009 ,pp. 234-237. [4] Kuramochi Y.,Matsuzawa A. and Kawabata M., “A 0.05-mm2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS” IEEE Asian Solid-State Circuits Conf.(ASSCC.) Jul. 2007, pp. 224 - 227. [5] Wenbo Liu and Yun Chiu, “An Equalization-Based Adaptive Digital Background Calibration Technique for Successive Approximation Analog-to-Digital Converters,” in 7th IEEE Int. Conf. ASIC, 2007 ,pp. 289-292. [6] Behzad Razavi, “Principles of Data Conversion System Design,” New York: IEEE Press,1995. [7] Behzad Razavi, “Design of Analog COMS Intergrated Circuits,” McGraw-Hill Companies, Inc. 2001 [8] Hsin-Hung Ou and Bin-Da Liu, “A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques,” in Proc. ISCAS , May. 2005 ,pp. 1972-1975. [9] Kazuaki Deguchi, Naoko Suwa, Masao Ito, Toshio Kumamoto, and Takahiro Miki, “A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 10, Oct .2008 [10] A. Rossi and G. Fucili, “Nonredundant successive approximation register for A/D converters,” Electron. Lett., vol. 32, no. 12, Jun. 1996, pp. 1055–1057. [11] Andrew M. Abo and Paul R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp.599-606 May 1999. [12] Yanfei Chen, Xiaolei Zhu, Tamura H., Kibune M., Tomita Y., Hamada T., Yoshioka M., Ishikawa K., Takayama T., Ogawa J., Tsukamoto S. and Kuroda T., “Split capacitor DAC mismatch calibration in successive approximation ADC,” Custom Integrated Circuits Conf.(CICC), Sep. 2009, pp. 279-282. [13] Murmann B. “A/D Converter Trends: Power Dissipation, Scaling and Digitally Assisted Architectures, ” Custom Integrated Circuits Conf.(CICC), 2008, pp. 105-112. [14] Yoshioka M., Ishikawa K., Takayama T., Tsukamoto S., “A 10-b 50-MS/s 820uW SAR ADC With On-Chip Digital Calibration” IEEE J. Biomedical Circuits and System, vol. 4, no. 6, pp.410-416 Dec. 2010. [15] 陳柏予, “雙倍取樣100MS/s 10位元之全雙端雙管線式類比數位轉換器,”國立中興大學電機工程學系碩士班研究生畢業論文,中華民國九十七年一月。zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/6318-
dc.description.abstract本論文描述一10位元910KHz取樣率連續逼近式類比數位轉換器(SAR ADC),並加入校正機制進行校正,校正內部電容不匹配,使電路能達到之有效位元數(ENOB)提高。 在加入校正電路之前,輸入頻率為0.1倍取樣率之正弦波訊號,量測得到其ENOB為6.55bit,SNR值為41.19dB,INL為-16.69LSB~2.52LSB,DNL為-1LSB~9.919LSB,功率消耗4.58mW。 加入校正電路後,並改善取樣保持電路與類比數位電源區隔後,電路後模擬得到其結果:ENOB為8.78,SNR值為54.62dB,INL為-1.267LSB~3.66LSB,DNL為-1LSB~1.56LSB,功率消耗1.34mW。 在本論文校正機制中在某些情形會產生錯誤,將其錯誤改善後比較其電路前模擬之結果:改善前ENOB為9.74,SNR為61.44dB,改善其錯誤後ENOB為9.91,SNR為60.39dB。zh_TW
dc.description.tableofcontents摘要.....................................................I Abstract.................................................II 目錄.....................................................III 表目錄...................................................V 圖目錄...................................................VI 第一章 緒論..............................................1 1-1 研究動機............................................1 1-2 研究方向............................................1 1-3 內容大綱............................................3 第二章 類比數位轉換器架構簡介...........................4 2-1 快閃式(Flash) ADC...................................4 2-2 管線式(Pipeline)ADC.................................4 2-3 連續逼近式(Successive approximation Register)ADC....5 第三章 ADC重要參數......................................7 3-1 解析度(Resolution)..................................7 3-2 微分非線性與積分非線性 (Differential Nonlinearity, Integral Nonlinearity)...................................9 3-3 訊號雜訊比(Signal to Noise Ratio, SNR)..............9 3-4 有效位元數(Effective Number of Bits, ENOB)..........10 3-5 Figure of Merit, FOM................................10 第四章 SAR ADC電路實現(SAR7)............................11 4-1 取樣保持電路........................................11 4-1.1 取樣保持電路架構與電路考量........................11 4-1.2 取樣保持電路模擬..................................13 4-2 電壓比較電路........................................14 4-2.1 前級放大器(Preamp)與電路模擬......................15 4-2.2 比較器(Comparator)與電路模擬......................16 4-3 電容式數位類比轉換器(DAC capacitor array)...........18 4-3.1 DAC電路考量.......................................18 4-3.2 DAC電路模擬.......................................19 4-4 控制邏輯(Control Logic).............................21 4-4.1 數位電路控制機制..................................21 4-4.2 電路模擬..........................................23 4-5 整體電路模擬........................................24 4-5.1 整體電路前模擬(pre-simulation)....................24 4-5.2 電路佈局(Layout)..................................27 4-5.3 整體電路後模擬(post-simulation)...................28 4-6 電路量測............................................30 4-6.1 測試方法與測試儀器................................31 4-6.2 測試結果..........................................32 第五章 SAR ADC校正機制..................................37 5-1 校正方式............................................37 5-2 原電容值偵測與並聯校正電容方式......................38 5-2.1 電容分壓校正......................................38 5-2.1 電容交換充電校正..................................39 5-3 校正電路架構........................................41 5-3.1 校正電容架構......................................42 5-3.2 校正邏輯控制......................................42 5-3.3 校正機制的錯誤....................................45 第六章 校正電路實現與改善...............................46 6-1 取樣保持電路改善....................................46 6-2 數位電路類比電路隔離................................48 6-3 加入校正電路........................................49 6-3.1 校正機制模擬......................................49 6-3.2 校正對整體電路影響................................51 6-3.3 加入校正電路之電路佈局............................54 6-4 校正機制改善........................................57 6-4.1 校正機制改善後電路架構............................57 6-4.2 校正機制改善後電路模擬............................57 6-5 晶片測試............................................60 第七章 結論及未來展望...................................63 參考文獻.................................................64 附錄一:SARC下線報告.....................................66 附錄二:SARC量測報告.....................................79zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-0908201116083600en_US
dc.subjectADCen_US
dc.subject類比數位轉換器zh_TW
dc.subjectDACen_US
dc.subjectComparatoren_US
dc.subjectCalibrationen_US
dc.subjectCapacitor arrayen_US
dc.subject數位類比轉換器zh_TW
dc.subject比較器zh_TW
dc.subject校正zh_TW
dc.subject電容陣列zh_TW
dc.title可自我校正電容陣列之單端輸入十位元連續逼近式類比數位轉換器zh_TW
dc.titleA Self-calibrating 10-bit Single End Successive Approximation Register ADCen_US
dc.typeThesis and Dissertationzh_TW
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.fulltextno fulltext-
item.languageiso639-1en_US-
item.grantfulltextnone-
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