Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6327
DC FieldValueLanguage
dc.contributor張順志zh_TW
dc.contributor楊清淵zh_TW
dc.contributor.advisor林維亮zh_TW
dc.contributor.author蘇修緯zh_TW
dc.contributor.authorSu, Shiou-Weien_US
dc.contributor.other中興大學zh_TW
dc.date2012zh_TW
dc.date.accessioned2014-06-06T06:37:53Z-
dc.date.available2014-06-06T06:37:53Z-
dc.identifierU0005-0908201116180300zh_TW
dc.identifier.citation[1]C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010. [2]H.-C. Hong, G.-M. Lee, “A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2161-2168, Oct. 2007. [3]W. Y. Pang, C. S. Wang, Y. K. Chang, N. K. Chou and C. K. Wang, "A 10-bit 500-KS/s Low Power SAR ADC with Splitting Comparator for Bio-Medical Applications," IEEE Asian Solid-State Circuits Conference, pp. 149-152, Nov. 2009. [4]S. Jiang, M. A. Do, K. S. Yeo, and W. M. Lim, “An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit, ”IEEE Trans Circuits Syst. I Reg. Papers, vol. 55, no. 6, pp. 1430-1440, Jul. 2008. [5]A.-M. Abo, P.-R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May. 1999. [6]C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process,” in IEEE Symp.VLSI Circuits Dig., Jun. 2009, pp. 236-237 [7]M. van Elzakker, E. van Tuijl, P. Geraedts, et al., “A 1.9μW 4.4fJ/Conversionstep 10b 1MS/s Charge-Redistribution ADC,” ISSCC Dig. Tech. Papers, pp. 244-245, Feb., 2008. [8]J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 0.5-V 1- μW successive approximation ADC,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1261–1265, Jul. 2003. [9]J. J. Kang and M. P. Flynn, “A 12b 11MS/s successive approximation ADC with two comparators in 0.13μm CMOS,” IEEE Symposium on VLSI Circuits, Jun. 2009, pp. 240-241. [10]N. Verma and A. P. Chandrakasan, “An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2007, pp. 1196–1205. [11]C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18µm CMOS,” in IEEE Symp.VLSI Circuits Dig., Jun. 2010, pp. 241-242 [12]C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” ISSCC Dig. Tech. Papers, pp. 386-387, Feb. 2010. [13]M. Scott, B. Boser, and K. Pister, “An Ultra Low-Energy ADC for Smart Dust,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1123-1129, July 2003. [14]S. W. M. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13- μmCMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 574–575. [15]M. Yip and A. P. Chandrakasan, “A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2011, pp. 190–192. [16]Behzad Razavi, “Principles of data conversion system design” John Wiley & Sons, Inc., 1995. [17]Mark Burns and Gordon W. Roberts , “An introduction to mixed-signal IC test and measurement” New York Oxford, 2001 [18]李國銘,“Design of An Ultra-low Power Successive Approximation Analog-to-Digital Converter for Wireless Sensor Networks” 國立交通大學碩士論文,中華民國九十五年七月。 [19]范揚航,“Estimating the influence of substrate noise on a SAR ADC in pre-layout simulation” 國立清華大學碩士論文,中華民國九十八年九月。zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/6327-
dc.description.abstract本篇論文描述一個適用於生醫系統之低功率消耗連續逼近式類比數位轉換器的設計,其建構在二進制加權電容之架構上。相較於一般差動式架構,本篇論文採用國立成功大學電機系發表之單一電容切換程序來減少功率消耗。在TSMC 0.18µm Mixed-Signal 1P6M Polycide 1.8V製程下,達到1M Sample/s之取樣頻率。 SARD5之晶片面積為1.13mm2,供應電壓為2伏特。取樣頻率(Sample Rate)為1MS/s ,輸入弦波其頻率為490KHz(振幅為0.1V~1.9V)之情況下量測結果如下:其微分非線性誤差(DNL)為-0.3509 LSB ~ 2.1983 LSB、積分非線性誤差(INL)為-6.387 LSB ~ 5.858 LSB、SNDR=53.74 dB與ENOB=8.64 bits,整體消耗功率約為0.3607 mW,FOM為904 fJ/conversion-step。 SARD7之晶片面積為1.13mm2,供應電壓為2伏特。取樣頻率(Sample Rate)為1MS/s,輸入弦波其頻率為490KHz(振幅為0.1V~1.9V)之情況下量測結果如下:其微分非線性誤差(DNL)為-0.4311 LSB ~ 0.3484 LSB、積分非線性誤差(INL)為-0.5214 LSB ~ 0.5268 LSB、SNDR=57.66 dB與ENOB=9.29 bits,整體消耗功率約為0.327 mW,其FOM為522 fJ/conversion-step,相較於SARD5有明顯的改進。zh_TW
dc.description.tableofcontents摘要....................................................I Abstract................................................II 目錄....................................................III 圖目錄..................................................X 表目錄..................................................XIV 第一章 緒論............................................1 1.1 研究動機...........................................1 1.2 研究方向...........................................1 1.3 內容大綱...........................................3 第二章 連續逼近式類比數位轉換器簡介....................4 2.1 連續逼近式類比數位轉換器(SAR-ADC)的基本架構........4 2.2 連續逼近式類比數位轉換器(SAR-ADC)的基本原理........4 2.3 低功率消耗DAC電容陣列之文獻探討....................6 2.4 差動式連續逼近式類比數位轉換器之改善...............7 第三章 連續逼近式類比數位轉換器之實現..................10 3.1 整體電路架構.......................................10 3.2 取樣保持電路模擬分析...............................10 3.3 比較器電路模擬分析.................................15 3.4 SAR控制邏輯電路分析................................19 3.5 數位類比轉換器(DAC)分析............................23 3.6 整體SAR-ADC分析....................................26 第四章 佈局考量以及電路模擬............................31 4.1 佈局考量...........................................31 4.1.1 比較器電路之佈局考量.............................31 4.1.2 DAC電容陣列之佈局考量............................33 4.1.3 整體電路之佈局考量...............................33 4.2 電路模擬...........................................36 4.2.1 取樣保持電路之模擬結果...........................36 4.2.2 比較器電路之模擬結果.............................37 4.2.3 DAC電路之模擬結果................................38 4.2.4 整體SARD5之模擬結果..............................39 第五章 量測結果........................................44 5.1 量測環境...........................................44 5.2 量測結果 (I).......................................46 5.3 量測結果 (II).......................................50 第六章 改善效能之方法及成果............................55 6.1 改善效能之方法.....................................55 6.2 改善效能之模擬成果.................................60 6.3 SARD7之量測結果....................................65 6.4 文獻比較...........................................70 第七章 結論及未來方向..................................71 7.1 結論...............................................71 7.2 未來方向...........................................71 參考文獻................................................72 附錄....................................................74 附錄A SARD7 下線報告..................................74 附錄B SARD7 量測報告..................................85zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-0908201116180300en_US
dc.subjectMonotonic Capacitor Switchingen_US
dc.subject單一電容切換zh_TW
dc.subjectADCen_US
dc.subjectSuccessive Approximationen_US
dc.subject類比數位轉換器zh_TW
dc.subject連續逼近zh_TW
dc.title單一電容切換程序之差動式十位元連續逼近式類比數位轉換器zh_TW
dc.titleA 10-bit Successive Approximation Register ADC With Monotonic Capacitor Switching Procedureen_US
dc.typeThesis and Dissertationzh_TW
item.languageiso639-1en_US-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.grantfulltextnone-
item.fulltextno fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
Appears in Collections:電機工程學系所
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