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標題: H.264/AVC畫框內預測之超大型積體電路架構設計與實現
VLSI Architecture Design and Implementation for H.264/AVC Intra Frame Prediction
作者: 柯彥吉
Ken, Yen-Chi
關鍵字: VLSI Architecture Design;H.264;H.264;Intra Frame;畫框內預測;超大型積體電路
出版社: 電機工程學系所
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在畫框內編碼方面, 我們的架構主要是提供量化值和最佳預測模式給編碼器編碼,可達HDTV的水準(1280*720,30張/秒)。在H.264方面,則提供重建畫面給下一張畫面作移動估測。

H.264 is a new image standard. This paper is to research Intra Frame Prediction of H.264. It processes intra spatial prediction by using boundary pixels of nearing block. In baseline of H.264, Intra Frame Prediction has 9 4*4 spatial prediction and 4 16*16 spa-tial prediction in luminance, and 4 8*8 spatial prediction in chrominance. Hence, how to decide the best prediction mode is an important part. On the other hand, 4*4 spatial pre-diction must be reconstructed and predicted next 4*4 block. In reconstruction process, it needs 4*4 DCT, Quantize, Inverse Quantize, Inverse 4*4 DCT, and reconstruction. 16*16 spatial prediction and 8x8 spatial prediction don't have cause of process, but the different of the best prediction passes through 4*4 DCT, these Dc value of each 4*4 block are gathered, and process them by Hadamard transform, quantization. By the way, they can be coded by entropy coding.
In algorithm, we based on reference software of H.264, we simulated reference soft-ware, decide that how to select the best prediction mode according to performance of image and hardware cost. We disable the prediction mode of most hardware cost ac-cording to simulation result. This process let me get trade-off between image perform-ance and hardware cost.
In hardware architecture design, we propose intra prediction generator which gener-ates 16 pixels per cycle, it can support 9 prediction modes by changing its input data. In transform architecture, we use direct form architecture to match our system. It has throughout of 16 pixels and 8 pixels per cycle, and provides adaptability for our design. First, we implement each block (including intra prediction generator, DCT, IDCT, Q, IQ, Hadamard, and I Hadamard), get almost delay information of each block, and design data flow of system. We implement it into hardware finally.
In intra frame coding, our architecture provides quantization values and the best pre-diction mode for entropy coding. It can meet standard of HDTV (1280*720, 30Frames/sec). In H.264, it provides reconstruction frames to process motion estimation for next current frame.
其他識別: U0005-1508200601262600
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