Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6414
標題: 應用於射頻前端接收器之高性能子電路研製
Implementation of RF Receiver Sub-circuits to Achieve High Performance
作者: 王繼豪
Wang, Chi-Hao
關鍵字: Frequency divider;除頻器;VCO;RF Receiver;LNA;Mixer;壓控振盪器;射頻前端接受器;低雜訊放大器;混波器
出版社: 電機工程學系所
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摘要: 
本論文主要分為四個主題,第一個主題為壓控振盪器的設計,第一個振盪器為使用gm-boosted技巧降低Colpitts震盪器的起振條件,並以低電壓操作達到低功率消耗,再使用四階的LC-Tank來增加輸出功率降低相位雜訊,電路以TSMC 0.18 um 製程完成晶片製作,量測操作頻率為15 GHz,相位雜訊在1MHz偏移量為-105.7dBc/Hz,消耗功率為2.1mW。第二個振盪器使用可變電容串聯電感的架構,共振電容的損耗改善相位雜訊,電路以TSMC 0.18 um 製程完成晶片製作,量測操作頻率為22.8 GHz,相位雜訊在1MHz偏移量為-111.76dBc/Hz,消耗功率為12.5mW。
第二個主題為注入鎖定除二除頻器的設計,第一個除頻器使用電阻串聯的架構,除了增加注入電晶體的轉導值,也可降低LC-tank的Q值,增加除頻範圍,電路以TSMC 0.18 um 製程完成晶片製作,量測輸入頻率為7 GHz至13 GHz,除頻比率為60%,消耗功率為17mW。第二個除頻器使用四階LC-Tank的架構,來增加鎖定範圍,並在訊號路徑上串聯電阻,增加注入電晶體轉導值與降低LC-tank的Q值,進一步提升鎖定範圍,電路以TSMC 0.18 um 製程完成晶片製作,量測輸入頻率為26.4 GHz至32.6 GHz,除頻比率為21%,消耗功率為12.5mW。第三個除頻器使用同相位雙注入技巧來提升注入訊號電流,增加鎖定範圍,並使用電流再利用的架構來降低功率消耗,電路以TSMC 0.18 um 製程完成晶片製作,量測輸入頻率為24.5 GHz至29 GHz,除頻比率為16.8%,消耗功率為1.26mW。
第三個主題為注入鎖定除三除頻器的設計,第一個除頻器由單平衡式的混波器與環型注入鎖定除二除頻器所構成,利用環型除頻器較小輸入功率仍能維持較大鎖定範圍的特點並以差動注入的方式輸入訊號提升除三除頻器的鎖定範圍,電路以TSMC 0.18 um 製程完成晶片製作,量測輸入頻率為56 GHz至57 GHz,消耗功率為14.8mW。第二個除頻器在混波器與除二除頻器中加入放大器,使訊號從混波器輸出後放大,再進入除二除頻器,增加鎖定範圍,電路以TSMC 0.18 um 製程完成晶片製作,量測輸入頻率為17.2 GHz至21.9 GHz,消耗功率為24.4mW。
第四個主題為前端電路整合的設計,第一級使用疊接式共源極低雜訊放大器,提供高增益與低雜訊,第二級使用主動式分波器,提供增益並將單端訊號轉為差動訊號輸出至第三級,第三級混波器使用Current-beeling的技巧,來降低電流轉導級的閃爍雜訊,達到低雜訊的設計。

The thesis includes four topics. The first topic describes the voltage control oscillator(VCO). The first VCO uses gm-boosted technique to reduce the startup condition, and operate at low voltage for low power consumption. Using Fourth-order LC-Tank to increase the output power to lower the phase noise. The circuit operated at 15 GHz, phase noise -105.7dBc/Hz at 1MHz offset, power consumption is 2.1mW, using TSMC 0.18 um technology to fabricate the chip.The second VCO use admittance transforming technique to improve the phase noise. The circuit operated at 22.8 GHz, phase noise -111.76 dBc/Hz at 1MHz offset, power consumption is 12.5 mW, using TSMC 0.18 um technology to fabricate the chip.
The second topic describes the 2:1 injection-locked frequency dividers(ILFD). The first ILFD implement the topology, which used series resistance to increase the injection transistors' transconductor and decrease quality factor of LC-tank for wide locking range. The chip implementation used TSMC 0.18 um technology, the measured input frequency is 7 GHz to 13 GHz, the locking range ratio is 60%, power consumption is 17 mW. The second ILFD uses Fourth-order LC-Tank network to increase locking range. Also implement the series resistance to increase the injection transistors' transconductor and decrease quality factor of LC-tank for wider locking range. The chip implementation used TSMC 0.18 um technology, the measured input frequency is 26.4 GHz to 32.6 GHz, the locking range ratio is 21%, power consumption is 12.5 mW. The third ILFD use double injection technique to increase locking range and a current re-used architecture to decrease power consumption. The chip implementation used TSMC 0.18 um technology, the measured input frequency is 24.5 GHz to 29 GHz, the locking range ratio is 16.8 %, power consumption is 1.26 mW.
The third topic describes the 3:1 injection-locked frequency dividers. The first one adopts a mixer and a 2:1 injection-locked frequency divider. By using the ring divider which can be maintained in a larger locking range at small input power. The differential input signal can enhance the locking range of 3:1 divider. The chip implementation used TSMC 90 nm technology, the measured input frequency is 56 GHz to 57 GHz, power consumption is 14.8 mW. The second one enhance the locking range by using an amplifier to magnify the output signal from mixer. The chip implementation used TSMC 0.18 um technology, the measured input frequency is 17.2 GHz to 21.9 GHz, power consumption is 24.4 mW.
The last topic is the design of the reciver. The first stage is a cascade common gate low noise amplifier(LNA),which offer high gain and low noise. The second stage is an active balun, which provide gain and divide the single-end signal to differential signal. The third stage a mixer, which used Current-beeling technique to improve the flicker noise.
URI: http://hdl.handle.net/11455/6414
其他識別: U0005-1408201110291400
Appears in Collections:電機工程學系所

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