Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6464
標題: 高性能新穎T型閘極複晶矽薄膜電晶體之研究
Study on the Novel High Performance T-Shaped-Gated Poly-Si TFTs
作者: 吳俊諭
Wu, Chun-Yu
關鍵字: poly-Si TFT;複晶矽薄膜電晶體;T-Gate;selective side-etching;T型閘極;選擇性側向蝕刻
出版社: 電機工程學系所
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Lewis, “Analysis of leakage currents in poly-silicon thin film transistors,” in IEDM Tech. Dig., 1993, pp. 385-388 [2.4] M. Yazakis, S. Takenaka and H. Ohshima, “Conduction Mechanism of Leakage Current Observed in Metal-Oxide-Semiconductor Transistors and Poly-Si Thin-Film Transistors,” J. Appl. Phys., vol. 31, pp. 206-209, 1992 [2.5] M. Rodder and, D. A. Antoiadis, “Comparsion of different techniques for passivation of small-grain polycrystalline-Si MOSFET's,” IEEE Trans. Electron Devices, vol. 6, pp. 570-575, 1985 [2.6] M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, and I. Policicchio, “Floating body effects in polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 44, pp. 2234-2241, 1997 [2.7] S. D. Brotherton, “Polycrystalline silicon thin film transistors,” Semiconduct. Sci. Technol., vol. 10, pp. 721-738, 1995 [2.8] M. Koyanagi, H. Kurino, T. Hashimoto, H. Mori, K. Hata, Y. Hiruma, T. Fujimori, I-Wei Wu, and A. G. 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Chiang, “Physical mechanisms for short channel effects in polysilicon thin film transistors,” IEDM 89, pp. 349-352, 1989 [2.14] S. Yamada, S. Yokoyama and M. Koyanagi, “Two-dimensional device simulation for avalanche induced short channel effect in poly-Si TFT,” IEDM 90, pp. 859-862, 1990 [2.15] M. Hack and A. G. Lewis, “Avalanche-induced effects in polysilicon thin-film transistors,” IEEE Electron Device Lett., vol. 12, pp. 203-205, 1990 [2.16] Z. Xiong, H. Liu, C. Zhu, and J. K. O. Sin, “A novel self-aligned offset-gated polysilicon TFT using high-k dielectric spacers,” IEEE Electron Device Lett., vol. 25, pp. 194-195, Apr. 2004 [2.17] K. Nakazawa, K. Tanaka, S. Suyama, K. Kato, and S. Kohda, “Lightly doped drain TFT structure for poly-Si LCD's,” SID Tech Dig., 1990, pp. 311-314 [2.18] K. R. Olasupo, W. Yarbrough, and M. K. Hatalis, “The effect of drain offset on current-voltage characteristics in sub micron polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 43, no. 8, pp.1306-1308, Aug. 1996 [2.19] T. Y. Huang, I. W. Wu, A. G. Lewis, A. Chiang, R. H. Bruce, “ A Simpler 100-V Polysilicon TFT with Improved Turn-on Characteristics,” IEEE Electron Device Lett., vol. 11, pp. 244-246, 1990 [2.20] K. Tanaka, K. Nakazawa, S. Suyama, and K. Kato, “Characteristics of field-induced-drain (FID) poly-Si TFT's with on/off current ratio,” IEEE Trans. Electron Devices, vol. 39, pp. 916-919, 1992 [2.21] K. Tanaka, S. Suyama, and K. Kato, “Influence of Field-Induced Drain on the Characteristics of Poly-Si Thin-Film Transistor using a Self-Aligned Double Spacer Process,” Jpn. J. Appl. Phys., vol. 43, pp. 897-900, 2004 [2.22] C. M. Yu, H. C. Lin, C. Y. Lin, K. L. Yeh, T. Y. Huang, T.F. Lei, “Self-aligned fabrication of thin-film transistors with field-induced drain,” Solid-State Electronics, vol. 46, pp. 1091-1095, 2002 [2.23] H. W. Hwang, C. J. Kang and Y. S. Kim, “A novel structured polysilicon thin-film transistor that increases the on/off current ratio,” Semicond Sci. Technol., 18, pp845-849, 2003 [2.24] K. M. Chang, Y. H. Chung, G. M. Lin, J. H. Lin, and C. G. Deng, “A Novel High-Performance Poly-Silicon Thin Film Transistor with a Self-Aligned Thicker Sub-Gate Oxide near the Drain/Source Regions,” IEEE Electron Device Lett., vol. 22, pp. 472-474, 2001 [2.25] J. h. Park, and O. Kim, “A novel self-aligned poly-Si TFT with field-induced drain by the damascene process,” IEEE Electron Device Lett., vol. 26, pp. 249-251, 2005 chapter 3 [3.1] J. h. Park, and O. Kim, “A novel self-aligned poly-Si TFT with field-induced drain by the damascene process,”IEEE Electron Device Lett., vol. 26, pp. 249-251, 2005 [3.2] A. C. Adams, “Plasma deposition of inorganic films,” Solid State Techno., vol.26, no.4, pp. 135-139, 1983 [3.3] C. Yin, P. C. H Chan, M. Chan, “An air spacer technology for improving short channel immunity of MOSFETs with raised source/drain and high-/spl kappa/ gate dielectric,” IEEE Electron Device Lett., vol. 26, pp. 323-325, 2005 [3.4] M. Togo, A. Tanabe, A. Furukawa, K. Tokunaga, T. Hashimoto, “A gate-side air-gap structure (GAS) to reduce the parasitic capacitance in MOSFETs,” in VLSI Technology Digest, pp. 38-39, 1996 [3.5] B. Shieh, K. C. Saraswat, J. P. McVittie, S. List, S. Nag, M. Islamraja, R.H. Havemann, “Air-gap formation during IMD deposition to lower interconnect capacitance,” IEEE Electron Device Lett., vol. 19, pp. 16-18, Jan. 1998. [3.6] S. Zhang, C. Zhu, Sin J.K.O., Li J.N., Mok P.K.T, “Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass,” IEEE Trans. Electron Devices, vol. 47, pp. 569-575, 2000 [3.7] A. G. Lewis, I. W. Wu, T. Y. Huang, M. Koyanagi, A. Chlang and R. H. Bruce, “Small geometry effects in N- and P- channel polysilicon thin film transistors,” IEDM 88, pp. 260-263, 1988 [3.8] A. G. Lewis, T. Y. Huang, I. W. Wu, R. H. Bruce, A. Chiang, “Physical mechanisms for short channel effects in polysilicon thin film transistors,” IEDM 89, pp. 349-352, 1989 [3.9] S. Yamada, S. Yokoyama and M. Koyanagi, “Two-dimensional device simulation for avalanche induced short channel effect in poly-Si TFT,” IEDM 90, pp. 859-862, 1990 [3.10] M. Hack and A. G. Lewis, “Avalanche-induced effects in polysilicon thin-film transistors,” IEEE Electron Device Lett., vol. 12, pp. 203-205, 1990 [3.11] M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi and K. Natori, “Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFET,” IEEE Trans. Electron Devices, vol. 37, pp. 2015-2020, 1990 [3.12] H. C. Cheng, F. S. Wang, and C. Y. Hung, “Effect of NH3 Plasma Passivation on N-Channel Polycrystalline Silicon Thin-Film Transistors,” IEEE Trans. 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摘要: 
在本篇論文中,我們利用選擇性側向蝕刻的技術成功地製作T型閘極複晶矽薄膜電晶體,最特別的是我們把具有最低介電質常數的材料(真空)嵌進在靠近複晶矽薄膜電晶體汲極與源極的上方,以降低汲極端接面的大電場。與傳統的複晶矽薄膜電晶體比較,本論文製作的T型閘極複晶矽薄膜電晶體擁有優越的電性,除了漏電流大幅的下降之外,此結構在元件導通時,能夠利用副閘極感應大量的載子,降低汲極源極的串聯電阻而維持極高驅動電流能力,所以導通與關閉電流的比例也能提升10倍。

此外,我們還模擬T型閘極複晶矽薄膜電晶體汲極接面的等電位線分布狀況。與傳統複晶矽薄膜電晶體不同的是,T型閘極結構能舒緩靠近汲極端等電位線分布,所以汲極端接面的大電場也能明顯的下降。本實驗還研究不同副閘極長度與不同真空厚度對T型閘極複晶矽薄膜電晶體的影響,由於T型閘極結構能夠利用未摻雜的偏移區降低水平電場,同時利用等效於相當厚的副閘極氧化層降低垂直電場,因此不論增加副閘極長度或提高真空厚度都能更有效降低漏電流,然而導通電流卻也隨之下降,這是因為通道中所感應的載子濃度減少,增大了汲極源極的串聯電阻,導致導通與關閉電流的比例無法提升。我們也發現T型閘極複晶矽薄膜電晶體因為降低了汲極端電場強度而有較不明顯的轉折效應(kink effect),因而有較大的輸出阻抗與電壓增益。

本實驗中,我們也研究了複晶矽薄膜電晶體的短通道效應,我們發現傳統複晶矽薄膜電晶體的臨界電壓會隨著通道長度縮短而劇烈下降,而T型閘極結構卻能夠有效的抑制此現象。另外,T型閘極結構也擁有較大的汲極崩潰電壓,以及在熱載子效應的可靠度測試下,T型閘極結構的臨界電壓漂移與導通電流減少、漏電流增加程度都比傳統複晶矽薄膜電晶體來的輕微,這些都是因為此結構可以有效的減緩汲極端接面的大電場,進而呈現出較佳的電性。值得一提的是本實驗所製作的T型閘極複晶矽薄膜電晶體製程簡單、且與傳統複晶矽薄膜電晶體所需的光罩數目都是一樣的。

In this thesis, we have successfully fabricated T-Shaped-Gated polycrystalline silicon thin film transistors (hereafter is called T-Gate TFTs) by using selective side- etching process. In particular, the vacuum gaps (the lowest dielectric constant material) are in-situ embedded in this T-Gate structure near the source and drain region to reduce the high drain electric field. Experimental results reveal that the T-Gate TFTs have excellent electrical performance. The leakage current of T-Gate TFT is decreased about two orders compared with the conventional TFTs. Moreover, the on-current can still be maintained by the sub-gate during the on-state operation, and the on/off current ratio of T-Gate is about 10 times higher than conventional one.

We compare the simulated electrostatic potential contours of the T-Gate TFT and the conventional TFT. It is shown obviously that in the T-Gate TFT, the electrostatic potential contours at channel surface near the drain region relaxed remarkably. Consequently, an obvious alleviation of electric field near the drain junction is obtained by using T-Gate structure, and it is consistent with the experimental results

Furthermore, the influences of vacuum gap thickness and sub-gate length of T-Gate TFTs are studied in this thesis. As a result, the off-state leakage current of T-Gate TFTs can be further reduced by increasing the vacuum gap thickness or stretching the sub-gate length. This is because the lateral electric field of T-Gate TFT can be relaxed by the undoped offset region, and the vertical electric field of T-Gate TFT can be relieved by the effective thicker sub-gate dielectric. However, the on-current of T-Gate TFTs also decrease seriously due to the raising of parasitic source/drain resistance, and bring about the degradation of on/off current ratio. It is also found that T-Gate TFT can suppress the kink effect significantly, and therefore offer higher voltage gain than conventional one.

In this experiment, short channel effect is also studied by analyzing characteristics of T-Gate TFTs with various channel length. It is shown that threshold voltage roll-off of T-Gate TFTs is less pronounced than that of conventional counterparts. Moreover, the T-Gate TFTs also have larger drain breakdown voltage and high long-term hot carrier reliability. All of these indicate that the drain electric field is alleviated in T-Gate TFTs. It is worth to note that T-Gate TFT is fabricated only by using a simple selective side-etching without any troublesome process and any additional masks.
URI: http://hdl.handle.net/11455/6464
其他識別: U0005-1707200619500900
Appears in Collections:電機工程學系所

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