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標題: 設計應用於CMOS技術之注入鎖定頻率除頻器
Design of Injection-Locked Frequency Dividers in CMOS Technology
作者: 葉嘉豪
Ye, Jia-Hao
關鍵字: Injection-Locked Frequency Dividers;注入鎖定頻率除頻器
出版社: 電機工程學系所
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本論文分為三大主題,第一個主題為研究四相位壓控振盪器,先利用次諧波電路將振幅以及相位達到兩倍的輸出訊號的,再利用雙推式的原理將兩倍頻訊號組合成四倍頻訊號做回授,最後達到四相位的輸出。以TSMC 0.18um製成完成晶片製作,量測範圍為7.233 GHz至8.562 GHz,相位雜訊在1MHz的偏移量為-105.6dBc/Hz,功率消耗為1.65mW。
第二個主題為三種不同除率的注入鎖定除頻器設計,第一種為除二電路,利用轉導放大的技巧,以及並聯電晶體的差動雙注入方式,來增加注入訊號的轉導以及降低共振腔的品質因子,增加除頻器的鎖定範圍。以TSMC 0.18um製成完成晶片製作,量測的輸入頻率範圍為13.2 GHz至18.8 GHz,除頻範圍為35%,功率消耗為4mW。第二種為除三電路,使用注入鎖定除二除頻器以及雙平衡式的混頻器來完成除三的動作,其中電路均利用current bleeding的技巧,在除二電路上,可以使得注入的訊號增大藉以增加鎖定範圍;在混頻電路上,增加驅動級的轉導來推動下一級的電路,以減低下一級負載效應的影響,以TSMC 0.18um製成完成晶片製作,量測的輸入頻率範圍為19.6 GHz至24.5 GHz,除頻範圍為22.2%,功率消耗為14.2mW。第三種為四相位的除四電路,此電路主要是應用在24 GHz的射頻收發機架構上,將19 GHz的訊號除四之後,以4.75 GHz的四相位輸出給四相位的混頻器做混頻使用,以TSMC 0.18um製成完成晶片製作,量測的輸入頻率範圍為17 GHz至19.8GHz,除頻範圍為15.13%,功率消耗為14.2mW。
第三個主題為77 GHz的低雜訊放大器,利用共平面波導的傳輸線來做輸出入的匹配以及級間的匹配元件,此傳輸線使用ground shielding的技巧來減少訊號傳輸時對於基底的損耗,因為高頻電路的寄生效應會比一般低頻電路來的明顯,所以在加以探討電晶體的尺寸以及偏壓點的選擇,以達到最好的增益以及雜訊指數的表現,以TSMC 90nm製成完成晶片製作,模擬結果輸入以及輸出的反射係數均達到-10dB以下,增益S21為17.6dB,反向隔離度S12為-42dB,雜訊指數為6.1dB,其線性度之1dB之增益壓縮點為-17.7dBm,三階交調點為-7dBm左右,電路整體功率消耗為26.7mW。
其他識別: U0005-1508201115570600
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