Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6535
DC FieldValueLanguage
dc.contributor.advisor張振豪zh_TW
dc.contributor.advisorChen-Hao Changen_US
dc.contributor.author許家禎zh_TW
dc.contributor.authorHsu, Chia-Chenen_US
dc.date2005zh_TW
dc.date.accessioned2014-06-06T06:38:27Z-
dc.date.available2014-06-06T06:38:27Z-
dc.identifier.urihttp://hdl.handle.net/11455/6535-
dc.description.abstract近幾年來,無線區域網路全世界性快速地發展著;而提供高速傳輸服務之無線通訊系統成為重要的研究之一。但是無線網路在空氣中遭受到不可預期的傳輸影響,比如說通道的衰減,這些影響將降低接受到訊號的品質。為了要處理這些問題,在接收端設計一個同步電路是必要的。 在本論文中將針對時脈回復和載波回復設計一個同步電路,為了處理無線通訊系統中載波回復問題,將提出一個創新的利用座標旋轉理論為基礎的弦波疊代震盪器。整個架構的實現與驗證會利用FPGA (Virtex2 XC2V1500)和ASIC的UMC 0.18um 1P6M CMOS製程,供應電壓為1.8伏特。在AWGN雜訊下,整個電路可以回復600KHz的頻率偏移。zh_TW
dc.description.abstractIn recent years, Wireless Local Area Network (WLAN) access has rapidly been deployed and worldwide extended. The development of wireless systems for high data-rate transmission has become one of important researches. But the wireless network suffers unpredictable transmission degradation in the air, such as channel fading. These effects will degrade the received signals. To deal with these problems, it is necessary to design a synchronization circuit in receiver. In this thesis, the synchronization circuit for timing and CFO estimation is presented and the novel CORDIC-based Sinusoid Iteration Oscillator (CSIO) is proposed for CFO estimation in wireless communication. This architecture was implemented and verified using both FPGA with VirtexII XC2V1500 and ASIC with 0.18 μm 1P6M CMOS technology at a supply voltage of 1.8V. It recovers the 600 kHz frequency offset in an AWGN wireless system efficiently.en_US
dc.description.tableofcontentsContents 中文摘要 Ⅰ Abstract Ⅱ 誌謝 Ⅲ Contents Ⅳ List of Figures Ⅶ List of Tables Ⅹ Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 OFDM Based WLAN System 4 2.1 OFDM Technique 4 2.1.1 Modulation by IFFT / FFT 6 2.1.2 Guard Interval and Cyclic Prefix 8 2.2 Overview of IEEE 802.11a Standard 10 2.2.1 Physical Layer 10 2.2.2 PPDU Format 11 2.2.3 Modulation Mapping 14 2.3 Block Diagram for IEEE 802.11a Baseband Transmission 15 Chapter 3 Synchronization Circuit Design 18 3.1 Design Hypotheses 18 3.2 Timing Estimation 19 3.2.1 Frame Detection 19 3.2.2 Symbol Boundary Detection 22 3.3 Carrier Recovery 25 3.3.1 Coarse CFO Estimation 26 3.3.2 Fine CFO Estimation 28 3.3.3 Phase Correction 29 Chapter 4 Hardware Implementation 32 4.1 Implementations of Timing Estimation 32 4.1.1 Autocorrelation 33 4.1.2 Cross-Correlation and Peak Detector 36 4.2 Implementations of CFO Estimation 39 4.2.1 Coarse CFO Estimation 39 4.2.2 Fine CFO Estimation 47 4.3 Hardware Simulations 48 4.3.1 Gate-Level Simulation Results 50 4.3.2 FPGA Measurement 53 Chapter 5 Conclusion 56 Reference 57zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系zh_TW
dc.subjectOFDMen_US
dc.subject同步zh_TW
dc.subjectsynchronizationen_US
dc.subjecttiming recoveryen_US
dc.subjectcarrier recoveryen_US
dc.subject時脈回復zh_TW
dc.subject正交zh_TW
dc.subject區域zh_TW
dc.subject網路zh_TW
dc.subject電路zh_TW
dc.subject載波回復zh_TW
dc.title適用於正交分頻多工無線區域網路之同步電路的實現zh_TW
dc.titleRealization of synchronization for OFDM-based wireless LAN systemen_US
dc.typeThesis and Dissertationzh_TW
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.fulltextno fulltext-
item.languageiso639-1en_US-
item.grantfulltextnone-
Appears in Collections:電機工程學系所
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