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標題: 新型低電壓低功率CMOS算術單元設計
New Low-Voltage Low-Power CMOS Arithmetic Units Design
作者: 賴文中
chung, lai weng
關鍵字: xor;低電壓;full adder;compressor;low voltage;low power;低功率;加法器;壓縮器
出版社: 電機工程學系
本篇論文探討了許多算術運算電路的基本單元,包含XOR、XNOR、XOR-XNOR、2:1多功器、全加器、4-2 及5-2 壓縮器,我們採用正規法設計傳輸閘,使之可工作於較低電壓並確保所有信號皆為全擺幅。而從中找到了新的XOR及XNOR電路,其PDP比它者為小;也找到了三個全新較佳效能的XOR-XNOR電路。

Owing to popularity of portable products, low power design has became an important issue in the CMOS circuit design. Furthermore, the supply voltage has a quadratic contribution to the power dissipation. Reducing the supply voltage is an effective way of lowering power consumption.
Arithmetic operations are the most important operation in many electronic device applications. They play the core role of overall circuit. To lower the power consumption of Arithmetic circuits is the major job of low power circuit design.
In this thesis, we investigate the basic cells of arithmetic circuits, including XOR, XNOR, XOR-XNOR, 2:1 multiplexer, full adder, 4-2 and 5-2 compressors. In order to operate in the very low supply voltage, we design the basic gate using the formal design methodology of pass gate to guarantee that all signals are full swing. We find a new XOR and XNOR circuit that delay time and PDP are the lowest compared to the others. Furthmore, we also find three new XOR-XNOR circuits that have better performance. We use the structured approach to design full adders by the basic cells, twenty designs in all. Many of them outperform the performance of previous designs. We also propose a new logic structure for the full adder, which performance is better than the previous adders.
In the compressors design, a new architecture of 4-2 compressor, Arch4 is proposed, whose performance outperforms the previous ones. Besides, two new architectures of 5-2 compressor, Arch6 and Arch7, are proposed whose performance are better than the previous ones. Arch6 has the fewest transistor count while Arch7 has the lowest power consumption. Employing buffer insertion to break the long RC delay chain in Arch6 would enhance its performance about 5%. Finally a generalized N-2 compressor is also proposed.
Appears in Collections:電機工程學系所

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