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The Power Amplifier Design for WLAN 802.11a and 60GHz Millimeter-Wave Applications
|關鍵字:||CMOS;CMOS;CS;GaAs;IEEE WLAN 802.11a;IEEE WPAN 802.15.3c;Lange coupler;millimeter wave;power amplifier;power combination technique;共源極放大器;GaAs;IEEE WLAN 802.11a;IEEE WPAN 802.15.3c;藍基耦合器;毫米波;功率放大器;功率結合||出版社:||電機工程學系所||引用:|| B. Razavi, “RF Microelectronics,” Prentice Hall, 1997.  柯柏丞，”應用於雙頻帶系統之本地振盪訊號源電路設計”國立中興大學電機工程研究所碩士論文，中華民國九十七年。  D-Link技術團隊，”無線區域網路技術白皮書”，松崗，2005。  林育聖，”60-GHz與26-/77-GHz 雙頻帶CMOS被動元件及主動濾波器之研製”國立成功大學電機工程研究所碩士論文，中華民國九十八年。  A. Bourdouz, J. Nsenga, W. Van Thillo, F. Horlin, and L. Van der Perre, “Air Interface and Physical Layer Techniques for 60GHz WPANs,” Communucations and Vehicular Technology Symp, pp.112-146, Nov. 2006.  B. Sklar, “Digital Communications: Fundamental and Appllications, 2nd edition,” Prentice Hall, pp. 249, 2001.  http://domino.research.ibm.com/comm/research_projects.nsf/pages/mmwave.apps.html  Steve C. Cripps, “RF power amplifiers for wireless communications,” Artech House, 2006.  David M. Pozar, “Microwave engineering 3/e,” Willy, 2005.  M. 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本論文主題在於設計製作兼具線性度與效率之微波功率放大器，設計應用的頻段有IEEE WLAN 802.11a 之5.2GHz頻段與IEEE WPAN 802.15.3c之 60GHz頻段，採用了TSMC 0.18μm與90nm之CMOS製程，還有WIN GaAs 0.15μm pHEMT製程。以下依各章節進行概述並包含了各電路之設計與量測結果。
第三章主要設計一個應用於802.11a 5.2GHz頻段之全積體化0.18μm CMOS功率放大器，並分析多級功率放大器基於線性度考量之各級1-dB增益壓縮點配置情形。而電路架構為兩級的共源極放大器所組成，輸出級採用多顆電晶體並聯方式以提高輸出功率與增益。量測時在1.8V供應電壓下直流功耗為160mW，1-dB增益壓縮點輸出功率(OP1dB)為11 dBm，最大效率PAE為10.4%，線性功率增益為14.4dB，最後針對量測偏差以模型模擬進行量測結果驗證分析。
第四章製作了兩顆應用於802.15.3c之60GHz功率放大器，並且探討傳輸線的設計方法，兩顆晶片製程皆採用WIN GaAs 0.15μm pHEMT製程。第一顆晶片採兩級共源極放大器架構，在偏壓上以線性度為主要設計考量，在毫米波(Millimeter wave)之波長範圍下在晶片內部以微帶線(Microstrip line)實現所有匹配網路，量測頻率為60GHz時在5V供應電壓下直流功耗為211mW，1-dB增益壓縮點輸出功率(OP1dB)為12.3dBm，最大效率PAE為7.83%，線性功率增益為10.4dB。第二顆晶片為三級電路設計，三級在架構上分別為增益級、驅動級與功率輸出級，功率輸出級使用藍基耦合器(Lange coupler)實現功率結合技術，由此提高輸出功率。量測時有頻率漂移現象，因此功率掃描量測設定在63GHz操作頻率下。5V供應電壓下，直流功耗為472mW，1-dB增益壓縮點輸出功率(OP1dB)為13dBm，最大效率PAE為6.9%，線性功率增益為22.9dB，匹配網路也是以微帶線在晶片內部實現。
第五章以TSMC 90nm CMOS製程設計了一個應用於802.15.3c之60GHz 功率放大器。為達到足夠增益電路為三級電路設計，並且三級的偏壓準位設定由第一級開始遞減到第三級，如此可以提高整體效率又能兼顧線性度。在60GHz操作頻率下，模擬結果為：在1.2V的供應電壓下直流功耗為103mW，1-dB增益壓縮點輸出功率(OP1dB)為9dBm，最大效率PAE為19.3%，線性功率增益為10.3dB，匹配網路同樣以微帶線在晶片內部實現。
In this thesis, design of microwave power amplifiers (PAs) with both linearity and efficiency considerations is presented. Applications of our designs cover the bands including 5 GHz for IEEE WLAN 802.11a and 60GHz for IEEE WPAN 802.15.3c. The process technologies used in chip implementation are TSMC 0.18-μm CMOS, TSMC 90-nm CMOS, and WIN GaAs 0.15-μm pHEMT, respectively. The contents of this thesis are summarized as following, including circuits design and measurement results in each chapter.
In Chapter I, we brief the reaserch background and contents of this thesis.
In Chapter II, discussions about system specifications, design considerations, and design method for the power amplifiers are presented. And various types of power amplifiers are also introduced.
The subject of Chapter III is mainly focused on the design of a 5.2GHz fully integrated 0.18-μm CMOS power amplifiers for WLAN IEEE 802.11a application. The circuit architecture is cascading two common source stages, and using multiple transistors in parallel as the output stage to increase the output power and gain. The measured maximum power consumption is 160 mW under 1.8 V supply voltage. The output power of 1-dB gain compression (OP1dB) is 11 dBm. The maximum power added efficiency (PAE) is 10.4%, linear power gain is 14.4dB. Finally, we analyze the difference between post-simulation results and measurement results by a trouble- shooting and simulation model recreation process.
In Chapter IV, designs of two 60GHz power amplifiers for IEEE 802.15.3c application are presented and design methods of the transmission line are also discussed. Both designs are implemented by using WIN GaAs 0.15μm pHEMT process technology. The first chip adopts two cascading common source stages, and the main consideration of bias scheme is the linearity. We use the microstrip lines to achieve all the matching networks in the chip for the millimeter-wavelength range. The operating frequency is the 60GHz and the measured DC power consumption is 211mW under a 5 V supply voltage. The measured OP1dB of the first chip is 12.3dBm, the measured maximum PAE is 7.83%, and the linear power gain is 10.4dB. The second chip is composed of three stages, including the gain stage, the driver stage, and the output power stage. At the output power stage, the Lange couplers are adopted to achieve power dividing/combining functions and to increase the output power. Since we found there is a drift of the operating frequency, therefore the input frequency is set to 63GHz in power sweep measurements. DC consumption of the second chip is 472mW under a 5 V supply voltage. The measured OP1dB is 13dBm, the maximum PAE is 6.9%, and the linear power gain is 22.9dB. The same microstrip line is adopted for matching networks within the chip.
In Chapter V, we present a 60GHz PA for IEEE 802.15.3c application by using TSMC 90-nm CMOS process technology. In order to achieve the required gain, the circuit adopts three-stage design. The bias level subsequently decreases from the first stage, and this can improve the overall efficiency while maintaining linearity. In 60GHz frequency, the simulated DC power consumption is 103mW under 1.2V supply voltage. The simulated OP1dB is 9dBm, the maximum PAE is 19.3%, and the linear power gain is 10.3dB. Again, matching network is made of the microstrip lines in the chip.
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