Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6575
標題: 使用重對齊責任週期校正器的低抖動延遲鎖定迴路
A Low Jitter Delay-Locked Loop with a Realignment Duty Cycle Corrector
作者: 李文益
Li, Larry
關鍵字: Delay-Locked Loop;延遲鎖定迴路;DLL;Realignment Duty Cycle Corrector;Duty Cycle Corrector;DCC;RDCC;Low Jitter;Jitter;責任週期校正器;反相器;校正器;電晶體;低功率;變異;低抖動
出版社: 電機工程學系
摘要: 
傳統的延遲定迴路會遭遇到責任週期變異與時脈抖動的問題,本論文提出了一個新的架構,在傳統的延遲鎖定迴路的輸出加入一個重對齊責任週期校正器,以解決責任週期變異與時脈抖動的問題。本論文提出的重對齊責任週期校正器,可以使延遲鎖定迴路的輸出維持在50%的責任週期。由四個電晶體與兩個反相器組成的重對齊責任週期校正器,具有低功率消耗、高操作頻率、低晶片面積的特性。此外,本論文採用”重對齊”的技巧以降低輸出時脈的抖動,也就是使用參考時脈訊號與鎖定訊號做一重對齊的動作,因此,鎖定訊號的時脈抖動會被有效的降低。本論文提出的延遲鎖定迴路經由台積電0.35-微米金氧半技術來設計與製作,且模擬結果也顯示,輸出的責任週期可以被控制在50%,而在3.3伏之工作電壓與250百萬赫茲的操作頻率之下,相較於傳統的延遲鎖定迴路,其時脈抖動可以有效降低61%。

In this thesis, a new delay-locked loop (DLL) architecture is proposed to effectively improve the DLL jitter performance. A novel realignment duty cycle corrector (RDCC) is proposed for the DLL. The RDCC circuit can make the output waveform of the DLL maintain a 50% duty cycle in a lock mode. The RDCC circuit has advantages of low power consumption, small chip area and high operating frequency. The proposed DLL adopts the clean ref-clock signal and the locked signal to do the “realignment” operation, which improves the jitter performance. The DLL is designed using the TSMC 0.35um 2P4M CMOS technology. HSPICE simulation results show that the proposed DLL jitter is effectively reduced 61% at 250MHz with a 3.3V supply.
URI: http://hdl.handle.net/11455/6575
Appears in Collections:電機工程學系所

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