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標題: 2.4GHz 可適性全數位頻率合成器
A 2.4GHz All-Digital Adaptive-Locked Frequency Synthesizer
作者: 黃名毅
Huang, Ming-Yi
關鍵字: All-Digital Frequency Synthesizer;全數位頻率合成器
出版社: 電機工程學系所
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Chen, “A 3.3V all digital phase-locked loop with small DCO hardware and fast phase lock” Circuits and Systems, 1998. ISCAS 98. Proceedings of the 1998 IEEE International Symposium on Volume 3, 31May-3 June 1998 Page(s):554-557 Vol3. [18]J. S. Chiang and K. Y. Chen, “The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock” Circuit and System II: Analog and Digital Signal Processing, IEEE Transactions on Volume 46, Issue7, July 1999 Page(s):945-950 [19]Yong Shim, Youngkwon Jo, Soohwan Kim and Kwangiun Cho, “A register controlled delay locked loop using a TDC and a new fine delay line scheme” Cricuits and Systems, 2006 ISCAS 2006. Proceedings, 2006 IEEE International Symposium on 21-24 May 2006. [20]Robert Bogdan Staszewski and Poras T. Balsara, “All-digital frequency synthesizer in deep-submicron CMOS”, John Wiley and Sons, INC., New Jersey, 2006. [21]G. Reehal,“A Digital Frequency Synthesizer Using Phase Locked Loop Technique”, M.S. Thesis, Ohio State University, 1998. [22]B. Razavi,“Monolithic Phase-Locked Loops and Clock Recovery Circuits” IEEE 1996. [23]V. Kratyuk, P.K. Hanumolu, K. Mayaram, and U. K. Moon, “A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range,” IEEE 2007 Custom Integrated Circuits Conference, Sept. 2007, pp. 305-308 [24]N. D. Dalt, E. Thaller, P. Gregorius, and L. Gazsi, “A Compact Triple-band Low-jitter Digital LC PLL with Programmable Coil in 130-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 40, no. 7, pp. 1482-1490, July 2005. [25]R.B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P.T. Balsara, “1.3V 20 ps Time-to-digital Converter for Frequency Synthesis in 90-nm CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 3, pp. 220-224, March 2006. Bibliography 119 [26]V. Kratyuk, P.K. Hanumolu, K. Ok, K. Mayaram, and U. K. Moon,“A Digital PLL with a Stochastic Time-to-digital Converter,” in Proc. Symposium on VLSI Circuits Digest of Technical Papers, 2006, pp. 31-32 [27]R. Tonietto, E. Zuffetti, R. Castello, and I. Bietti, “A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter,” in Proceedings of the 32nd European Solid-State Circuits Conference (ESSCIRC), Sept. 2006, pp. 150-153 [28]V. Ramakrishnan, and P.T. Balsara, “A Wide-range, High-resolution, Compact, CMOS Time to Digital Converter,” in Proceedings of the 19th International Conference on VLSI Design, Jan. 2006. [29]M. Lee and A. A. Abidi, “A 9 b, 1.25 ps Resolution Coarse-fine Time-to-digital Converter in 90 nm CMOS that Amplifies a Time Residue,” IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 769-777, April 2008. [30]J. Tierney, C. M. Rader, and B. Gold, “A digital frequency synthesizer,” IEEE Trans. Audio Electroncoust. vol. AU-19, no. 1, pp. 48-57, Mar. 1971. [31]Jim Dunning, Gerald Garcia, Jim Lundberg, and Ed Nuckolls,“An ALL-Digital Phase-Locked Loop with 50-cycle Lock Time Suitable for High Performance Microprocessors”, IEEE Journal of Solid-State Circuits, Vol.30, no.4, pp.412-422, Apr. 1995. [32]Ching-Che Chung and Chen-Yi Lee, “An All-Digital Phase-Locked Loop for High-Speed Clock Generation,” IEEE Journal of Solid-State Circuit, Vol. 38, NO. 2, Feb. 2003, pp.347-351 [33]Pao-Lung Chen, Ching-Che Chung and Chen-Yi Lee, “ An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications” IEEE International Symposium on. Circuits and Systems, 2005. ISCAS 2005. vol. 27, 4875 - 4878, May. 2005. [34]Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda and Muneo Fukaishi, “A 2.1-to-2.8 GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter ” IEEE Journal of Solid-State Circuit, vol. 45, no. 12, Dec. 2010. [35]S. Y. Yang, W. Z. Chen, and T. Y. Lu, “A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 578-586, Mar. 2010. [36]P.-L. Chen, C.-C. Chung and C.-Y. Lee, “An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications,” IEEE International Symposium on Circuits and Systems, vol. 5, pp. 4875-4878, May 2005. [37]S. Y. Lin and S. I. Liu, “A 1.5 GHz All-Digital Spread-Spectrum Clock Generator” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3111-3119, Nov. 2009. [38]C.-C. Chung and C.-Y. Lee, “An all-digital phase-locked loop for high-speed clock generation,” IEEE J. Solid-State Circuits, vol. 38, pp. 347-351, Feb. 2003. [39]Wong Man Chun, “A 1.8V 2.4GHz Monolithic CMOS Inductor-less Frequency Synthesizer for Bluetooth Application” the Hong Kong University of Science and Technology, M. S. thesis, Aug. 2002.
第二部分則介紹目前三個種類的鎖相迴路,類比式的鎖相迴路,數位式的鎖相迴路以及全數位式的鎖相迴路。鎖相迴路的基本理論以及設計,且會針對一些常用到的相位偵測器、電荷幫浦、壓控振盪器作分類說明。第三部分,我們提出了一個全數位鎖相迴路,這電路中包含了bang-bang相位偵測器、數位控制電路、數位壓控振盪器以及頻率偵測器。在這架構中,一個二位元型態的全數位鎖相迴路需要較長的頻率獲取時間,因為相位頻率偵測器的輸出僅為+1 和-1,故提出一個有效的減少頻率獲取時間的演算法,在全數位鎖相迴路中的數位控制振盪器對於電源雜訊有很大影響。最後,我們實現一個可應用在ISM 頻帶全數位式鎖相迴路,相較於傳統技術,此電路不但能快速鎖定,且具有低相位雜訊的優點。而此電路是以0.18 微米的互補式金氧半製程作模擬,操作在2.4GHz,相位雜訊約-135dBc/Hz,晶片面積為1.1*1.2mm2。

Over the last decades, the orientation of the fabrication process is to shrink the scaling of the transistor. Scaling down the transistor will have less power consumption and faster operation frequency to design circuits. However, it has extra drawbacks for analog circuits, but it is more suitable for digital circuits. Therefore, digital equivalent implementations of analog circuits are more popular, such as the phase-locked loop and the clock and data recovery. The thesis will be divided into four parts.
First, the thesis describes an all-digital phase-locked loop for ISM frequency band in wireless communication.
The second part of this thesis introduces the analog phase-locked loop (APLL), digital phase-locked loop (DLL) and all-digital phase-locked loop (ADPLL), introducing the fundamentals of the phase frequency detector, the charge pump, the loop filter and the voltage control oscillator.
The third part primarily introduces an ADPLL. The ADPLL circuit contains a bang-bang type phase detector, a digital control circuit, a DCO and a frequency detector. The ADPLL needs long frequency acquisition time because the phase detector only has binary outputs, +1 and −1. The proposed algorithm can effectively reduce the frequency acquisition time. The supply noise toward the DCO has severely impact in ADPLL.
In the last part, we realize an ADPLL for frequency synthesis. The frequency synthesizer is simulated in TSMC 0.18 CMOS technology. Its operation frequency is 2.4GHz, the total power is 40mW, the phase noise is about -135dBc/Hz at 1MHz offset, and the total area is 1.1*1.2mm2
其他識別: U0005-1707201122225600
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