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標題: 無線網路接收端之腓特比解碼器硬體設計與實作
Design and Implementation of Viterbi Decoders for WLAN Receivers
作者: 謝憲慶
Hsien, Shien-Ching
關鍵字: Viterbi Decoder;腓特比解碼器
出版社: 電機工程學系所
引用: [1] 蘇韋禎, “IEEE 802.11a 基頻接收機之分集結合技術和外接收機的硬體設計,” 2003年碩士論文, 國立中正大學. [2] 黃品玄, “可規劃式維特比解碼器之設計與實現,” 2001年碩士論文, 國立中央大學. [3] 葉承淵, “具多目標式腓特比解碼器之矽智財產生器,” 2002年碩士論文, 國立台北科技大學. [4] 李家慶, “適用於無線區域網路接收端之腓特比解碼器實作” 2005年碩士論文, 國立中興大學. [5] 詹明華, “適應性腓特比解碼器的設計,” 1990年碩士論文, 國立台灣大學. [6] Shu Lin, J. Daniel, Jr. Costello, Error Control Coding Fundamentals and Applications, New Jersey, NJ:Prentice-Hall, 1983. [7] A. J. Viterbi, “Error Bounds for Convolutional Codes and an asymptotically optimum decoding algorithm,” IEEE Trans. Inform. Theory, vol. IT-13, No. 2, Apr. pp. 260-269, 1967. [8] G. D. Forney, Jr., “The Viterbi Algorithm,” Proc. IEEE, vol. 61, pp. 268-278, Mar. 1973. [9] G. D. Forney, Jr., “Convolution Codes II:Maximum Likelihood Decoding,” Control, 25, pp. 222-226, July. 1974. [10] D. J. Costello, Jr., “Free distance bounds for convolution codes,”IEEE Trans. Inf. Theory, IT-20, pp. 356-365, May. 1974. [11] J. A. Heller and I. M. Jacobs, “Viterbi Decoding for statellite and space communication,” IEEE Trans. Commun. Technol., vol. COM19, no. 5, pp. 835-848, Oct. 1971. [12] T. K. Truong, M.T. Shih, I. S. Reed, E. H. Satorius, “A VLSI design for a trace-back Viterbi decoder,” IEEE Trans. Commun. Vol. 40, pp. 616-624, Mar. 1992. [13] S. Ranpara, Dong-Sam Ha, “A low-power Viterbi decoder design for wireless communications applications,” IEEE Int. Conf. ASIC/SOC, pp. 377-381, Sept. 1999. [14] Jung-Gi Baek, Sang-Hun Yoon, Jong-Wha Chong, “Memory efficient pipelined Viterbi decoder with look-ahead trace back,” IEEE Int. Conf. Electronics,Circuit and Systems(ICECS), Vol. 2, pp. 769-772, Sept. 2001. [15] D.A.F. Ei-Dib, M.I. Elmasry, “Low-power Register-exchange Viterbi Decoder for High-speed Wireless Communications,” IEEE Int. Symp. Circuits and Systems (ICSAS), vol. 5, pp. 737-740, 2002. [16] D.A.F. Ei-Dib, M.I. Elmasry, “Modified Register-exchange Viterbi Decoder for Low-power Wireless Communications,” IEEE Trans. Circuits and Systems (ICSAS), vol. 51, pp. 371-378, 2004. [17] Yu-xin You, Jin-xiang Wang, Feng-chang Lai, Yi-zheng Ye, “VLSI design and implementation of high-speed Viterbi decoder,” IEEE Int. Conf. Electronics,Circuit and Systems and West Sino Expositions, Vol. 1, pp. 64-68, June. 2002. [18] P. A. Riocreux, L. E. M. Brackenbury, M. Cumpstey, S. B. Furber, “A low-power self-timed Viterbi decoder,” Int. Symp. Asynchronous Circuits and Systems, pp. 15-24, Mar. 2001. [19] M. Kawokgy, C.A.T. Salama, “Low-power asynchronous Viterbi decoder for wireless applications,” Int. Symp. Low power Electronics and Design(ISLPED), pp. 15-24, Mar. 2001. [20] IEEE Std. 802.11a, Jun, 1999. [21] IEEE Std. 802.11g, Jan, 2002.
近年來,行動通訊科技發展極為迅速,隨著VLSI快速發展,使得數位通訊系統的複雜設計變成可行,例如正交分頻多工(OFDM)的技術因此蘊育而生。為了降低多重路徑衰減(Multipath Fading)的問題,在高速傳輸速度下,要考慮資料的可靠性及正確性,可利用迴旋碼改善資料傳送時所發生的錯誤;在接收端,則用腓特比解碼器(Viterbi Decoder)實現。
本論文的目標是設計一個可運用於IEEE 802.11 a/g無線區域網路的64狀態點的腓特比解碼器。不同於其他科技文獻中設計腓特比解碼器所使用的方法,我們改良了暫存器交換(Register Exchange)的方式減少電路面積;在輸出端使用了合併(merge)的架構,藉由合併許多路徑的收斂方法,降低錯誤率得到我們所需要的輸出,並且採用Soft decision的技巧來改善位元錯誤率(bit error rate)的效能。
本論文所設計之(2, 1, 6)腓特比解碼器採用無線區域網路通訊協定IEEE 802.11 a/g標準的規格,並使用軟式決策來實作。比較之下,IEEE 802.11 a/g標準所需要最高的腓特比解碼器操作頻率約為90MHz,而合成與模擬結果顯示,我們使用TSMC 0.18μm CMOS 1P6M技術所設計的電路在200MHz的工作頻率之下,具有200Mbps之產出,且仍能穩定工作,符合IEEE 802.11 a/g的需求。

In the past few years, due to VLSI technology the development of mobile communication science and technology was extremely fast. Many complicated design of digital communication system become feasible. For example, the Orthogonal Frequency Division Multiplexing (OFDM) technology was emerged. In order to reduce the multi-path fading problem in high-speed transmission, the convolutional codes can be used to reduce the data error rate in transmitters for data reliability and accuracy, while a Viterbi decoder is used in the receiver.
The goal of this thesis is to design a 64-state viterbi decoder for IEEE 802.11a/g WLAN. Unlike the other viterbi decoders proposed in literatures we improve the method of register exchange to reduce the circuit area. In the mean time, the path merging method was also applied to extract the desired decoded data for reduced power consumption. Furthermore, the soft decision technique was adopted to improve the bit error rate.
In this thesis, a (2, 1, 6) Viterbi decoder was designed and implemented for Wireless LAN IEEE 802.11 a/g standards with Soft decision. The synthesis and simulation results showed that the proposed circuit can be operated at the clock frequency of 200MHz with 200Mbps. The power consumption is 31mW using TSMC 0.18 μm 1P6M CMOS technology, while the highest required clock frequency of the Viterbi decoder in WLAN IEEE 802.11 a/g was estimated to be about 90MHz.
其他識別: U0005-2007200622495700
Appears in Collections:電機工程學系所

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