Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6659
標題: 適用於無線區域網路接收端之腓特比解碼器實作
Implementation of A Viterbi Decoder For WLAN Receiver
作者: 李家慶
Lee, Ja-Qing
關鍵字: Viterbi;腓特比;Decoder;WLAN;解碼器;無線區域網路
出版社: 電機工程學系
摘要: 
本論文的目標是設計一個可運用於IEEE 802.11 a/g無線區域網路的64狀態點的腓特比解碼器。不同於其他科技文獻中設計腓特比解碼器所使用的方法,我們將設計的焦點放在分支計量單元的設計上,使得分支計量單元的電路面積節省了超過50%。除此之外,在相加-比較-選擇單元電路上,也運用了硬體共用的設計理念,使用64個子電路模組和回授緩衝器來架構我們的相加-比較-選擇單元電路模組,最後再使用暫存器交換的方式來建立我們的存活記憶單元電路。
本論文所設計之(2, 1, 6)腓特比解碼器採用無線區域網路通訊協定IEEE 802.11 a/g標準的規格,使用硬式決策,碼率為1/2。比較之下,IEEE 802.11 a/g標準所需要最高的腓特比解碼器操作頻率約為90MHz,而合成與模擬結果顯示,我們使用UMC 0.18m CMOS 1P6M技術所設計的電路在高達200MHz的工作頻率之下,仍能穩定工作,遠超過IEEE 802.11 a/g的需求。

This thesis proposes a 64-state Viterbi decoder for IEEE 802.11a/g WLAN. The difference from the other technical literatures of Viterbi decoder was the design of the BMU (Branch-Metric Unit) circuits reduces the chip area of the BMU more than 50%. In addition, with appropriate hardware sharing design, we only use 64 ACSU (Add-Compare-Select Unit) sub-modules and feed-back buffers to build the complete ACSU circuit. Finally, the SMU (Survivor-Memory Unit) circuit was proposed of the register-exchange structure.
In this thesis, a (2, 1, 6) Viterbi decoder was designed based on Wireless LAN IEEE 802.11 a/g standards with hard decision and 1/2 coding rate. The synthesis and simulation results showed that the proposed circuit can be operated at the clock frequency of 200MHz using UMC 0.18 m 1P6M CMOS technology, while the highest required clock frequency of the Viterbi decoder in WLAN IEEE 802.11 a/g is about 90MHz.
URI: http://hdl.handle.net/11455/6659
Appears in Collections:電機工程學系所

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