Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6673
標題: 設計應用於頻率合成器之低功率子電路
Design of Frequency Synthesizer Sub-circuits to Acquire Low Power Operation
作者: 吳哲瑋
Wu, Zhe-Wei
關鍵字: Frequency Synthesizer;頻率合成器
出版社: 電機工程學系所
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[49] 柯柏承, "應用於雙頻帶系統之本地震盪訊號源電路設計"國立中興大學電機工程學系碩士學位論文,July 2010 [50]朱健綸, "電感興回授之低功率交錯耦合壓控振盪器, " 國立成功大學電機工程學系碩士學位論文,June 2006 [51]林曉彤, "應用於無線通訊之CMOS射頻微積電開關及2-GHz/5GHz 壓控振盪器RFIC之研究, "國立成功大學電機工程學系碩士學位論文,June 2004 [52]傅冠霖, " LC-Tank振盪器相位雜訊與消耗功率設計之權衡與寬頻注入鎖定除頻器, "國立中興大學電機工程學系碩士學位論文,Jan 2011 [53]陳臆聰, "24-GHz CMOS壓控振盪器與24-及60GHz除頻器之研製, "國立成功大學電機工程學系碩士學位論文,July2009 [54]黃振洋, "應用於無線區域網路於寬頻代系統之低雜訊放大器設計, "國立中央大學電機工程學系碩士學位論文,June 2005 [55]劉佳協, "60GHz毫米波CMOS射頻前端RFICs及關鍵被動元件之研究設計, "國立成功大學電腦與通信工程學系碩士學位論文,July 2007 [56]郭信智, "應用於60-GHz CMOS毫米波射頻接收機前端電路之研製, "國立成功大學電腦與通信工程學系碩士學位論文,July 2008
摘要: 
本論文以實現壓控振盪器電路設計為主,主要是以設計PLL內所需之子電路,所以本論文內所設計的為壓控振盪器,注入鎖定除二除頻器,注入鎖定除三除頻器,分別以三個主要章節講述其電路原理、模擬結果與最後量測結果。
第二章主要設計一個具有寬頻壓控範圍之壓控振盪器,其電路設計概念上主要利用了兩個技巧:第一為電晶體並聯的方式來達到增加整體電路的轉導值的方法,使得電路較容易達到振盪條件,第二是源極退化電容架構,利用電晶體的寄生電容來降低整體電路的電容值,來達到較寬的可調範圍。晶片使用TSMC 0.18μm CMOS 製程所製作。量測時在供應電壓1V下直流功耗為10.6mW;可調範圍為27.54~30.38GHz ,當振盪於27.54 GHz時量得知相位雜訊為-103.168 dBc/Hz@1MHz frequency offset。
第三章主要設計具有寬除頻範圍且較小的消耗功率的除二除頻器,其電路設計主要為使用電流再利用的技巧來達到消耗功率較小的方法,因為此電路為PMOS和NMOS疊接,因此兩個MOS共用一路電流,進而達到減少功率消耗。另外再使用電壓電流雙注入的方式來達到增加注入的電流,使得鎖定範圍較大。晶片使用TSMC 0.18μm CMOS 製程所製作。量測時在供應電壓1.6V下直流功耗為2.247mW。當輸入訊號功率為0dBm時,量得之可鎖定頻率範圍為18.3~25.2GHz。
第四章主要設計除三除頻器電路,主要為利用相差180度的訊號產生一個兩倍頻的訊號再與輸入的三倍頻混頻而達到除三的效果,此方法與另一種使用除二除頻器再加上一個混頻器的方法較不同,因此可以造成較小的面積。
第五章主要設計為應用於60GHz的低雜訊放大器,第一級為雜訊考量,所以使用共源極的架構來做第一級,如此可以使得整體電路的雜訊較小,第二級為了使得增益提升,因此再多串接一級共源極的架構,而最後一級為電流再利用架構,因此除了可以再提升一些增益外,也因為使用了此架構,所以可以減少功率的損耗。晶片使用TSMC 90 nm CMOS製程製作,模擬時在供應電壓1.2V下直流功耗為30.192mW。
URI: http://hdl.handle.net/11455/6673
其他識別: U0005-1708201120200300
Appears in Collections:電機工程學系所

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