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Design and Analysis of Frequency Synthesizers with High-performance Oscillators using an Integrated Transformer-Based Tunable Inductor Technique
|關鍵字:||Frequency Synthesizer;振盪器;Oscillator;Tunable Inductor;頻率合成器;可調電感||出版社:||電機工程學系所||引用:|| B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000.  B. Razavi, RF Microelectronics, Prentice Hall, 1998.  Neil H.E. Weste, K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd edition, Prentice Hall, 2000.  C. Patrick Yue, S. Simon Wong, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's”, IEEE J. Of Solid-State Circuits, Vol. 33, No.5, pp. 743-752, MAY 1998.  B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2003.  Floyd M. Gardner, Phaselock Techniques, 3rd edition, New York: Wiley& Sons, 2005.  F. Gardner, “Charge-Pump Phase-Lock Loops”, IEEE Trans. Communications, Vol. 28, pp. 1849-1858, Nov. 1980.  M. Van Paemel, “Analysis of a charge-pump PLL: a new model”, IEEE Trans Communications, Vol.42, pp.2490-2498, July 1994.  M. Soyuer and R. G. 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Samavati, H.R. Rategh, M. del Mar Hershenson,; M. Xu; C.P. Yue, D.J. Eddleman, M.A. Horowitz, T.H. Lee, “Low-power dividerless frequency synthesis using aperture phase detection”, IEEE J. Of Solid-State Circuits, Vol. 33, pp. 2232 - 2239, Dec. 1998.  Ching-Yuan Yang; Shen-Iuan Liu, “Fast-switching frequency synthesizer with a discriminator-aided phase detector,” IEEE J. Of Solid-State Circuits, Vol. 35, pp. 1128-1136, Aug. 2000.||摘要:||
第二部分將探討有關於傳統電感-電容式壓控振盪器的架構，及使用電容式變容器的缺點分析，提出可變電感架構，並使用積體化變壓器的概念實現。針對利用積體化變壓器構成的可變電感架構進行分析，對其特性加以探討，並將此理論應用於壓控振盪器中，分別提出實現於兩種架構：增益控制振盪器與轉導控制振盪器，皆以0.18μm CMOS 製程製造。增益控制振盪器分為兩組，分別操作於3GHz 與7GHz 的頻帶，在1MHz 頻率偏移處相位雜訊為-125dBc/Hz 與-113dBc/Hz，最低功率消耗可為4.8mW 與9mW，FoM 達到-188 dBc/Hz 與-180 dBc/Hz。轉導控制振盪器可操作於5GHz 頻帶，在1MHz 頻率偏移處相位雜訊為-121dBc/Hz，功率消耗約為9mW，FoM 為-187 dBc/Hz。
最後一部份將探討頻率合成器的設計，可分為兩個主題，第一部分為使用可變電感所實現的增益控制振盪器應用於頻率合成器中，此頻率合成器的除頻器為雙模組除頻器，並加上三角積分調變器進行調變，使其能夠達到除小數的功能，其輸出頻率範圍3.74GHz~4.68GHz，工作電壓為1.8V時的功率消耗為67mW。另一部分則是將另外一種振盪器架構-轉導控制振盪器應用於頻率合成器中，此頻率合成器主要被設計能符合超寬頻通訊系統模式一的規格，且以快速鎖定與快速跳頻為主要設計訴求，並使用無除頻器的鎖相迴路達到此目的，其中使用到兩個鎖相迴路共用一除頻器以節省功率消耗，並進行模擬驗證此架構的可行性，本晶片以0.18μm CMOS製程製造，面積為1.4mm × 1.4mm，工作電壓為1.8V 時的功率消耗為89mW。
This thesis describes the feasibility study of inductive varactor realized with integrated transformer and frequency synthesis based on phase-locked loop technique. There are three major parts in this thesis discussed in detail.
The first part of the thesis would introduce the concept of phase-locked loop, and describe about how it operations. The differences between integer-N and fractional-N frequency synthesizer, in addition to the fractional-N one realized with delta-sigma modulator would be discussed. And then, the phase noise concept and its model together with the design of LC voltage controlled
oscillator would be mentioned.
The second part of this thesis discussed the traditional LC VCO applied capacitive varactors and its disadvantages. The thesis proposed the concept of inductive varactor. The proposed structures employ integrated transformers as
inductance with voltage-controlled value. The traditional approach of tuning the VCO oscillation frequency by capacitance variation would be sacrificed, and the proposed structure with induction variation will be applied to substitute for that. Two kinds of the VCOs are proposed. One is gain-controlled oscillator, and the other is transconductance-controlled oscillator. The measurement result of the first kind of the VCOs have phase noise at 1MHz offset from a 3GHz and 7GHz carrier of -125dBc/Hz and -113dBc/Hz, and the power consumption is about 4.85mW and 9mW. FoM is about -188 dBc/Hz and -180 dBc/Hz. The
second kind of the VCO has phase noise at 1MHz offset from a 5GHz band carrier of -121dBc/Hz, and the power consumption is about 9mW. FoM is about -187 dBc/Hz.
The last part of all, the work presents the frequency synthesizer based on PLLs. It divided into two parts of the work. The first one applied the gain-controlled oscillator, dual-modulus frequency divider and delta-sigma
modulator to realize a fractional-N frequency synthesizer. The output frequency ranges from 3.74GHz to 4.68GHz. It consumes 67mW from a 1.8V power supply. The other frequency synthesizer is based on transconductance
-controlled oscillator, which is designed to meet the OFDM UWB Mode-1 application specification. The frequency synthesizer is designed for fast locking and fast hopping application with dividerless architecture. In addition, this thesis discusses the problems of the SSB-mixer applied in the papers in the recent years. The two PLLs share one frequency divider to reduce power consumption. The chip is implemented in 0.18μm CMOS technology with the
die area 1.4mm × 1.4mm and consumes 89mW from a 1.8V power supply.
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