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Design of Driving Circuits for Low-Temperature Polycrystalline Silicon Thin-Film Transistor-Liquid Crystal Display
|關鍵字:||low-temperature polycrystalline silicon;低溫多晶矽;thin-film transistor;liquid-crystal display;driving circuit;shift register;digital/analog converter;DC/DC converter;薄膜電晶體液晶顯示器;驅動電路;移位暫存器;數位類比轉換器;直流電壓轉換器||出版社:||電機工程學系||摘要:||
本論文探討以低溫多晶矽製程技術所製造之薄膜電晶體液晶顯示器之驅動電路設計，我們研發了新的移位暫存器(shift register)、數位類比轉換器(digital/analog converter)及直流電壓轉換器(DC/DC converter)。
在移位暫存器方面，考量到傳統控制訊號線及電路面積較大，所以設計新的移位暫存器，每一級移位暫存器只有兩個clock訊號及9個電晶體組成，能縮小電路面積，且半個clock週期能產生一個移位訊號，可提升pixel clock頻率為兩倍，此電路可應用於資料驅動電路(data driver circuit)及掃描驅動電路(scan driver circuit)內。
直流電壓轉換器仍是以外部電路提供驅動電路所需的電源，本論文提出新型互補式電荷幫浦(complementary charge pump)，在clock正負週期皆可輸出穩定電壓，四級的電荷幫浦可輸出-4VDD及+5VDD的電壓及高輸出供應電流，功率效率(power efficiency)達71 ％，可提供週邊驅動電路所需要的電壓源。
最後，電路實作驗證部分，以LTPS 1P2M 最小線寬為5 μm之低溫多晶矽製程技術來實現移位暫存器及數位類比轉換器，直流電壓轉換器由TSMC 0.35 μm CMOS 2P4M製程技術來實現。
In this thesis, the novel driving circuits of thin-film transistor-liquid crystal displays (TFT-LCDs), which included shift registers, digital/analog converters (DAC) and DC/DC converters, were developed by using low-temperature polycrystalline silicon (LTPS) technology.
For conventional shift registers, because larger circuit area or more controlled signals, a novel shift register consists of only two clock signals and nine transistors in an unit cell was proposed. The proposed shift registers decreased circuit area and double the frequency of the pixel clock. The novel shift register can apply for data drivers and scan drivers of LCDs.
For DACs, due to the conventional R-string DAC had larger area and the switch-capacitor type DAC (SC-DAC) takes longer conversion time, the resolution of TFT-LCDs was limited. For this reason, we developed a novel fast-switch-capacitor DAC (FSC-DAC) for LCD panels with higher resolution (XGA and above). For the FSC-DAC, the conversion time is only half of the conventional SC-DAC and the circuit area was decreased significantly compared with conventional R-String DAC.
The DC/DC converter was designed as external circuits. A novel complementary charge pump was proposed and it provided steady output voltage during positive and negative clock periods. The output voltages of the proposed four-stage charge pump were 5VDD and -4VDD for positive and negative polarity, respectively. The maximum power efficiency of the complementary charge pump reached to 71%.
Finally, the proposed shift register and the FSC-DAC were fabricated by using the 1P2M LTPS process technology and the design rule is 5 μm. The proposed DC/DC converter was fabricated by using the TSMC 0.35 μm 2P4M CMOS process technology.
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