Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6738
標題: 嵌入式無失真與近似無失真影像壓縮系統之設計與實現
Design and Implementation of an Embedded Lossless and Near Lossless Video compression system
作者: 呂銘維
Lyu, Ming-Wei
關鍵字: lossless compression;無失真影像壓縮;rate control;embedded system;流量控制;嵌入式系統
出版社: 電機工程學系所
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摘要: 
由於影像影的尺寸不段增加,大數據的無線網路傳輸已經帶來了巨大的挑戰,要如何舒緩如此龐大的頻寬且不能有影像損失即成了一個嚴峻的挑戰。而本論文主要的應用為無線投影播放系統,基於無失真壓縮技術的方式,結合軟硬體共設計概念實現壓縮系統於嵌入式平台上。而採用的方式則以高產量,高壓縮率,低運算複雜的的方式完成,因此本論文採用了單維度影壓壓縮並結合了色彩轉換機制、預測系統與錯誤補償、適應性Golomb 編碼器的方式完成整個系統。相較於相較於FELICS[1]則提升了49%的壓縮率,相較於JPEG-LS[2]則提升4.6%的壓縮率。於運算複雜度方面相較於JPEG-LS則只有他的72.4%的運算時間。

而本論文的第二部份在於提出一個Mixed Rate Control System的適應性演算法,藉由Golomb codec的檢查編碼特性跟在binary mode下使用三種不同編碼長度,藉著調整PSNR來達到符合符合限定的壓縮率,使的頻寬能正常傳輸。而於實驗結果表現出我們的rate control方法在保持於近無失真影像壓縮品質為大於50dB時有能力減少bit rate達13.2%。

我們所提出的嵌入式壓縮系統實驗於一組ARM926-EJS與Xilinx Spartan-3 FPGA平台上,分別對應到設計中的軟體與硬體部分。而軟體部分則實現了系統參數選擇與畫面資訊顯示。而為了提昇速度,將主要的運算核心放硬體電路。並考慮了資料相依性的問題,採用了管線化與平行化的方式提昇系統效能。而為了整合考量,設計中也加入了軔體設計,並採用Master Wrapper的方式提昇資料由軟體搬移至硬體的速度。基於CIC的MorPack平台,我們的系統可以於此嵌入式系統中顯示800X400的RGB影像並有11.43的fps,而除了FPGA平台外,我們也將此硬體做成了晶片,而晶片含有2組壓縮/解壓縮系統,此設計的gate count為153.5M並工作於200 MHz,換算系統效能可達顯示1920X1080的RGB影像並有67.42fps的系統效能。

The large data bandwidth demand due to the ever increasing video resolution has posed a big challenge on the wireless multimedia network. How to alleviate the communication bandwidth without suffering from any content loss is the key point to tackle such a challenge. Targeting on the application of wireless video playback projection, this thesis investigates on embedded lossless video compression schemes and presents a HW/SW codesign based implementation. The scheme is effective in compression efficiency and requires low computing complexity. The proposed scheme adopts a single-banded texture predictor and a color-correlation based transformation to enhance the efficiency. With the employment of techniques such as frame classification, prediction error feedback mechanism, smooth binary mode detector, and adaptive Golomb Codec, the proposed scheme can outperform the FELICS[1] scheme by 49% in terms of compression ratio. The performance edges against The JPEG-LS[2] and JPEG-LS are 4.6% and 72.4%, respectively.

In the second part of the thesis, a Mixed Rate Control System using an adaptive algorithm is proposed. By examining the coding property of Golomb codec and making use of 3 different coding lengths in binary mode, compression ratio can be adjusted to meet the bandwidth constraint with controlled PSNR loss. The experimental results show that our rate control scheme is capable of reducing the bit rate by 13.2% while maintaining a near lossless video quality with PSNR values greater than 50dB.

Our embedded Compression system is developed on a platform containing an ARM926-EJS processor and a Xilinx Spartan-3 FPGA. The design is partitioned into software and hardware sections. The software section implements the functions of coefficient control and frame information display. The hardware section realizes the computing kernel to achieve the speed up. Taking data dependence into account, the hardware design employs various techniques such as pipelining, parallel processing, and data sharing to improve the performance. Additional firmware design is also developed, which interfaces with the "Master Wrapper" to facilitate a high throughput data movement between the hardware and software sections. Based on CIC''s MorPack platform, our system can perform embedded video compression at a speed of 11.43 fps for 800X480 RBG images. Besides the FPGA prototyping, the hardware section design is also converted to a chip implementation. The chip design has a gate count of 153.5M and can operate at 200 MHz. The equivalent frame rate is 67.42 fps for 1920X1080 sized images.
URI: http://hdl.handle.net/11455/6738
其他識別: U0005-1808201120200900
Appears in Collections:電機工程學系所

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