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Orthogonal Frequency Division Multiplexing baseband Receiver Design for Next Generation Passive Optical Network
|關鍵字:||NG-PONs;次世代被動光纖網路;OFDM;baseband receiver;sampling frequency compensation;channel estimation & equalization;正交分頻多工技術;基頻接收機;取樣頻率補償;通道估測與等化||出版社:||電機工程學系所||引用:|| I. Takayanagi et al., “A 1 1/4 inch 8.3M pixel digital output CMOSAPS for UDTV application,” in IEEE ISSCC Dig. Tech. Papers, 2003,pp. 216–217.  Nishiguchi T., et al., 2007, Production and Live Transmission of 22.2 Multichannel Sound with Ultrahigh-definition TV, Presented at AES the 122nd Convention, 2007 May 5–8 Vienna, Austria.  ITU-T Rec. G.707/Y.1322 PDF, Network node interface for the synchronous digital hierarchy (SDH) (Geneva: International Telecommunications Union, January 2007). Accessed 2010-11-03.  ITU-T Rec. G.783 PDF, Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks (Geneva: International Telecommunications Union, March 2006). Accessed 2010-11-03.  ITU-T Rec. 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本論文中，次世代被動光纖網路(NG-PON)收發機研究，針對NG-PON系統平台可大致分成電子與光學的兩大部分。在光學方面，我們採用直接強度調變偵測(IMDD)的光電架構，且不使用任何光放大器或色散補償元件，來降低系統布建成本；而在電子方面，一般認為在電域中使用數位信號處理(DSP)解決訊號在光網路中的損耗，較在光域中補償低廉。此外，由於半導體雷射和光電檢光器的光電元件成本，常與可用的系統頻寬成正比，為進一步降低建構成本。我們採用正交分頻多工(OFDM)的調變機制，用以增加頻譜的使用率，並減少色散、偏極化等其他通道失真所帶來的影響。在64QAM的相同調變機制下，在低於2GHz的通道頻寬中，傳送資料量可達8.667Gbps。在鏈結網路方面，我們根據傳輸功率預算，定義出對應的系統規格，提出4GHz取樣頻率，八路平行操作在500MHz工作頻率的基頻架構，以符合高速電路的運算量。在基頻電路模組設計中，我們開發有效的平行同步電路設計，包含有封包偵測、FFT邊界偵測以及取樣頻率補償；另外，一個八路平行的64點FFT處理器和頻率域中的一階迫零等化器設計。最後，實現在配有高速串型鏈路RocketIO的Xilinx的Virtex 5 LTX平台驗證，發現操作頻率可達331 MHz，且運算的關鍵路徑多座落於快速傅立葉轉換(FFT)電路模組上。最後，我們將FFT模組再以UMC 90nm晶片實現，發現FFT電路在核心面積為1.64 x 1.64 mm2，功率消耗為54mW中，可達500 MHz的工作時脈頻率。
Due to the ever increasing demands on data communication bandwidth for services such as High Definition video and audio broadcast, on-line gaming, distance learning, and so on, traditional wired networks have failed to provide satisfactory services. In face of these emerging applications requiring high-data rate, real-time and multi-users services, Next-generation passive optical networks (NG-PONs), due to its spectral efficiency and cost effective implementation, is regarded as a promising solution.
In this thesis, the baseband transceiver design for the NG-PON is investigated. The NG-PON platform can be divided into the electrical and the optical sections. For the optical section, we assume an IMDD (intensity modulation and direct detection) optoelectronics architecture is adopted. No optical amplification and chromatic dispersion compensation measures are employed to reduce the system cost on the optical section. Instead, the optical network impairments are tackled in the electrical domain where the DSP solution is considered much less expensive than the counterpart in the optical domain. To further reduce the bandwidth, which is proportional to the cost of the opto-electrical conversion devices such as laser diode and photon detector, we adopt an OFDM architecture to enhance the spectrum efficiency. The OFDM architecture also provides an easy solution to the effects of chromatic dispersion, polarization mode dispersion and other fiber distortion. A uniform 64QAM modulation format is used in each tone and a data rate as high as 8.667Gbps can be delivered occupying a frequency bandwidth less than 2GHz. Starting with a network specs, the link budget is first calculated and baseband performance specs are derived accordingly. The system operates at a sampling frequency of 4GHz and an 8-way parallel baseband architecture working at 500MHz is developed to meet the computing demands. In the baseband module designs, we develop efficient parallel synchronization schemes covering packet detection, FFT boundary detection, sampling frequency offset compensation. A 8-way parallel 64-point FFT processor and a simple one-tap equalizer performed in the frequency domain using zero forcing strategy are also developed. The developed baseband transceiver design is implemented on a Xilinx Virtex 5 LTX rapid prototyping platform equipped with high speed serial links RocketIO. The implementation results show that the design can operate at 331MHz and the critical path delay is bounded by the FFT module. As FFT is the most computation intensive module in the baseband design, it is further implemented in chip using UMC 90nm process. The design occupies a 1.64 x 1.64 mm2 chip area and consumes 54 mW at the clock rate of 500 MHz.
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